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TMP86FS49FG

Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared

to “0” when SYSCK = “1”.

Note 2: *: Don’t care, TG: Timing generator

Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.

Note 4: Do not set IDLE and TGHALT to “1” simultaneously.

Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period

of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.

Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.

Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.

Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals

may be set after IDLE0 or SLEEP0 mode is released.

2.2.4 Operating Mode Control

2.2.4.1 STOP mode

STOP mode is started by setting STOP (Bit7 in SYSCR1) to “1”. During STOP mode, the following

status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers, the program status word and port output latches are all held in the

status in effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])

which started STOP mode.

STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be

selected with the RELM (Bit6 in SYSCR1).

Note 1: During STOP period (from start of STOP mode to end of warm up), due to changes in the external

interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately

after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before

enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.

(1) Level-sensitive release mode (RELM = “1”)

backup when the main power supply is cut off and long term battery backup.

System Control Register 2

SYSCR2

(0039H)

76

543

21

0

XEN

XTEN

SYSCK

IDLE

TGHALT

(Initial value: 1000 *0**)

XEN

High-frequency oscillator control

0: Turn off oscillation

1: Turn on oscillation

R/W

XTEN

Low-frequency oscillator control

0: Turn off oscillation

1: Turn on oscillation

SYSCK

Main system clock select

(Write)/main system clock moni-

tor (Read)

0: High-frequency clock

1: Low-frequency clock

IDLE

CPU and watchdog timer control

(IDLE1/2 and SLEEP1/2 modes)

0: CPU and watchdog timer remain active

1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)

TGHALT

TG control (IDLE0 and SLEEP0

modes)

0: Feeding clock to all peripherals from TG

1: Stop feeding clock to peripherals except TBT from TG.

(Start IDLE0 and SLEEP0 modes)

TENTATIVE