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TMP86FS49FG Datasheet(PDF) 29 Page - Toshiba Semiconductor

Part # TMP86FS49FG
Description  8 Bit Microcontroller
PDF  42 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS49FG Datasheet(HTML) 29 Page - Toshiba Semiconductor

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Page 27
TMP86FS49FG
2.2.4.4 SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).
The following is the methods to switch the mode with the warm-up counter (TC4, TC3).
(1) Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCK (Bit5 in SYSCR2) to switch the main system clock to the low-frequency clock
for SLOW2 mode.
Next, clear XEN (Bit7 in SYSCR2) to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before per-
forming the above operations. The timer/counter 6, 5, 4, 3 (TC6, TC5, TC4, TC3) can conveniently
be used to confirm that low-frequency clock oscillation has stabilized.
(2) Switching from SLOW1 mode to NORMAL2 mode
First, set XEN (Bit7 in SYSCR2) to turn on the high-frequency oscillation. When time for stabili-
zation (Warm up) has been taken by the timer/counter 4, 3 (TC4, TC3), clear SYSCK (Bit5 in
SYSCR2) to switch the main system clock to the high-frequency clock.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.
SET
(SYSCR2). 5
; SYSCR2<SYSCK>
← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR
(SYSCR2). 7
; SYSCR2<XEN>
← 0
(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET
(SYSCR2). 6
; SYSCR2<XTEN>
← 1
LD
(TC3CR), 43H
; Sets mode for TC4, TC3 (16-bit TC, fs for source)
LD
(TC4CR), 05H
LDW
(TTREG3), 8000H
; Sets warm-up time (Depend on oscillator accompanied)
DI
; IMF
← 0
SET
(EIRH). 1
; Enables INTTC4
EI
; IMF
← 1
SET
(TC4CR). 3
; Starts TC4, 3
:
PINTTC4:
CLR
(TC4CR). 3
; Stops TC4, 3
SET
(SYSCR2). 5
; SYSCR2<SYSCK>
← 1
(Switches the main system clock to the low-frequency clock)
CLR
(SYSCR2). 7
; SYSCR2<XEN>
← 0
(Turns off high-frequency oscillation)
RETI
:
VINTTC4:
DW
PINTTC4
; INTTC4 vector table
TENTATIVE



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