ADXL375 datasheet(12/32 Pages) AD

12 / 32 page

ADXL375

Data Sheet

Rev. 0 | Page 12 of 32

Trigger Mode

In trigger mode, the FIFO buffer accumulates samples, storing

the latest 32 samples from measurements of the x-, y-, and z-axes.

After a trigger event occurs, an interrupt is sent to the INT1 or

INT2 pin (determined by the trigger bit in the FIFO_CTL register),

and the FIFO_TRIG bit (Bit D7) is set in the FIFO_STATUS

The FIFO buffer keeps the last n samples (n is the value specified

by the samples bits in the FIFO_CTL register) and then operates

in FIFO mode, collecting new samples only when the FIFO buffer

is not full. A delay of at least 5 µs must elapse between the occur-

rence of the trigger event and the start of data readback from the

FIFO buffer to allow the buffer to discard and retain the necessary

samples.

Additional trigger events cannot be recognized until the part is

reset to trigger mode. To reset the part to trigger mode,

1. If desired, read data from the FIFO buffer (see the Retrieving

Data from the FIFO Buffer section).

Before resetting the part to trigger mode, read back the

FIFO data; placing the device into bypass mode clears the

FIFO buffer.

2. Configure the device for bypass mode by setting Bits[D7:D6]

at Address 0x38 to 00.

3. Configure the device for trigger mode by setting Bits[D7:D6]

at Address 0x38 to 11.

Retrieving Data from the FIFO Buffer

When the FIFO buffer operates in FIFO, stream, or trigger mode,

FIFO data can be read from the data registers (Address 0x32 to

Address 0x37). Each time data is read from the FIFO buffer, the

oldest x-, y-, and z-axis data is moved into the DATAX, DATAY,

and DATAZ registers.

If a single-byte read operation is performed, the remaining bytes

of data for the current FIFO sample are lost. Therefore, data for

all axes of interest must be read in a burst (multiple-byte) read

operation. To ensure that the FIFO buffer is empty (that is, all

new data has moved into the data registers), an interval of at

least 5 µs must elapse between the end of the readback from the

data registers and the start of a new read of the data registers or

the FIFO_STATUS register (Address 0x39). The end of a read

operation from the data registers is signified by the transition

from Register 0x37 to Register 0x38 or by the CS pin going high.

When SPI operation is enabled at a frequency of 1.6 MHz or

lower, the register addressing portion of the transmission provides

a sufficient delay to ensure that the FIFO buffer has completely

emptied. When SPI operation is enabled at a frequency higher

than 1.6 MHz, the CS pin must be deasserted to ensure a total

delay of 5 µs; otherwise, the delay is not sufficient. When SPI

operation is enabled at 5 MHz, the total delay necessary is at

most 3.4 µs.

When I2C mode is enabled on the part, the communication rate

is low enough to ensure a sufficient delay between FIFO reads.

SELF-TEST

The ADXL375 incorporates a self-test feature that effectively

tests its mechanical and electronic systems simultaneously. When

the self-test function is enabled (via the SELF_TEST bit in the

DATA_FORMAT register, Address 0x31), an electrostatic force

is exerted on the mechanical sensor.

This electrostatic force moves the mechanical sensing element in

the same manner as acceleration, and it is additive to the external

acceleration experienced by the device. This added electrostatic

force results in an output change in the x-, y-, and z-axes. Because

the electrostatic force is proportional to VS2, the output change

varies with VS.

The self-test response in the x- and y-axes exhibits bimodal

behavior and, therefore, is not always a reliable indicator of

sensor health or potential shift in device sensitivity. For this

reason, perform the self-test check in the z-axis.

Use of the self-test feature at data rates of less than 100 Hz or at

1600 Hz may yield values outside the limits shown in Figure 16.

For the self-test function to operate correctly, the part must be in

normal power operation (LOW_POWER bit = 0 in the BW_RATE

100 Hz to 800 Hz, or for a data rate of 3200 Hz (see Table 6).

For more information about the self-test feature, see the Using

Self-Test section.

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