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ADXL375 Datasheet(PDF) 17 Page - Analog Devices |
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ADXL375 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 32 page ![]() Data Sheet ADXL375 Rev. 0 | Page 17 of 32 Table 11. SPI Digital Input/Output Specifications Limit1 Parameter Test Conditions/Comments Min Max Unit DIGITAL INPUT Low Level Input Voltage (VIL) 0.3 × VDD I/O V High Level Input Voltage (VIH) 0.7 × VDD I/O V Low Level Input Current (IIL) VS = VDD I/O 0.1 µA High Level Input Current (IIH) VS = 0 V −0.1 µA DIGITAL OUTPUT Low Level Output Voltage (VOL) IOL = 10 mA 0.2 × VDD I/O V High Level Output Voltage (VOH) IOH = −4 mA 0.8 × VDD I/O V Low Level Output Current (IOL) VOL = VOL, MAX 10 mA High Level Output Current (IOH) VOH = VOH, MIN −4 mA PIN CAPACITANCE fIN = 1 MHz, VS = 2.5 V 8 pF 1 Limits based on characterization results; not production tested. Table 12. SPI Timing (TA = 25°C, VS = 2.5 V, VDDI/O = 1.8 V)1 Limit2, 3 Parameter Min Max Unit Description fSCLK 5 MHz SPI clock frequency tSCLK 200 ns Mark-space ratio (1/(SPI clock frequency)) for the SCLK input is 40/60 to 60/40 tDELAY 5 ns CS falling edge to SCLK falling edge tQUIET 5 ns SCLK rising edge to CS rising edge tDIS 10 ns CS rising edge to SDO/SDIO disabled tCS, DIS 150 ns CS deassertion between SPI communications tS 0.3 × tSCLK ns SCLK low pulse width (space) tM 0.3 × tSCLK ns SCLK high pulse width (mark) tSETUP 5 ns SDI/SDIO valid before SCLK rising edge tHOLD 5 ns SDI/SDIO valid after SCLK rising edge tSDO 40 ns SCLK falling edge to SDO/SDIO output transition tR4 20 ns SDO/SDIO output high to output low transition tF4 20 ns SDO/SDIO output low to output high transition 1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. 2 Limits based on characterization results, with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 3 The timing values are referred to the input thresholds (VIL and VIH) given in Table 11. 4 Output rise and fall times measured with capacitive load of 150 pF. tR and tF are not shown in Figure 25 to Figure 27. |
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