ADXL375 datasheet(14/32 Pages) AD

14 / 32 page

ADXL375

Data Sheet

Rev. 0 | Page 14 of 32

Inactivity Bit

The inactivity bit is set when acceleration less than the value stored

in the THRESH_INACT register (Address 0x25) is experienced

for more time than is specified by the TIME_INACT register

(Address 0x26) on all participating axes. Participating axes are

specified by the ACT_INACT_CTL register (Address 0x27). The

maximum value for TIME_INACT is 255 sec.

Watermark Bit

The watermark bit is set when the number of samples in the FIFO

buffer equals the value stored in the samples bits (Bits[D4:D0])

of the FIFO_CTL register (Address 0x38). The watermark bit

is cleared automatically when the FIFO buffer is read and the

FIFO contents return to a value below the value specified by the

samples bits.

Overrun Bit

The overrun bit is set when new data replaces unread data. The

precise operation of the overrun function depends on the FIFO

mode (see the FIFO Buffer section).

•

In bypass mode, the overrun bit is set when new data

replaces unread data in the data registers (Address 0x32

to Address 0x37).

•

In FIFO mode, stream mode, and trigger mode, the

overrun bit is set when the FIFO buffer is full.

The overrun bit is automatically cleared when the FIFO buffer

contents are read.

ADXL375 Datasheet(PDF) 14 Page - Analog Devices