ADXL375 datasheet(15/32 Pages) AD

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Data Sheet

ADXL375

Rev. 0 | Page 15 of 32

SERIAL COMMUNICATIONS

The ADXL375 supports I2C and SPI digital communications. In

both cases, the ADXL375 operates as a slave device. When the CS

pin is tied high to VDD I/O, I2C mode is enabled. The CS pin must

be tied high to VDDI/O or be driven by an external controller. If the

CS pin is left unconnected, the user may not be able to communi-

cate with the part. In SPI mode, the CS pin is controlled by the

bus master. In both SPI and I2C modes of operation, ignore data

transmitted from the ADXL375 to the master device during writes

to the ADXL375.

SPI MODE

The ADXL375 can be configured for 3-wire SPI mode or 4-wire

SPI mode, as shown in Figure 22 and Figure 23. Clearing the SPI

bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects

4-wire mode; setting the SPI bit selects 3-wire mode. The maxi-

mum SPI clock speed is 5 MHz with 100 pF maximum loading.

The timing scheme requires clock polarity (CPOL) = 1 and clock

phase (CPHA) = 1. If power is applied to the ADXL375 before the

clock polarity and phase of the host processor are configured, take

the CS pin high before changing the clock polarity and phase.

When using 3-wire SPI mode, it is recommended that the SDO

pin be either pulled up to VDD I/O or pulled down to GND via a

10 kΩ resistor.

PROCESSOR

D OUT

D IN/OUT

D OUT

ADXL375

SDIO

SDO

SCLK

Figure 22. 3-Wire SPI Connection Diagram

PROCESSOR

D OUT

D IN

D OUT

ADXL375

SDI

SDO

SCLK

Figure 23. 4-Wire SPI Connection Diagram

CS is the serial port enable line and is controlled by the SPI master.

This line must go low at the start of a transmission and high at the

end of a transmission, as shown in Figure 25 to Figure 27. SCLK

is the serial port clock and is supplied by the SPI master. SCLK

should idle high during a period of no transmission. In 4-wire

SPI mode, SDI and SDO are the serial data input and output,

respectively. In 3-wire SPI mode, SDIO functions as both the

serial data input and output. Data is updated on the falling edge

of SCLK and should be sampled on the rising edge of SCLK.

To read or write multiple bytes in a single transmission, the

multiple-byte bit (MB in Figure 25 to Figure 27), located after

the R/W bit in the first byte transfer, must be set. After the

set of eight clock pulses causes the ADXL375 to point to the next

pulses cease and CS is deasserted. To perform reads or writes on

different, nonsequential registers, CS must be deasserted between

transmissions and the new register must be addressed separately.

Figure 25 and Figure 26 show the timing diagrams for 4-wire

SPI writes and reads, respectively. Figure 27 shows the timing

diagram for 3-wire SPI reads or writes. For correct operation of

the part, the logic thresholds and timing parameters in Table 11

and Table 12 must be met at all times.

Use of the 3200 Hz and 1600 Hz output data rates is recom-

mended only with SPI communication speeds greater than or

equal to 2 MHz. The 800 Hz output data rate is recommended

only with communication speeds greater than or equal to 400 kHz,

and the remaining data rates scale proportionally. For example,

the minimum recommended communication speed for a 200 Hz

output data rate is 100 kHz. Operation at an output data rate above

the recommended maximum value may result in undesirable

effects on the acceleration data, including missing samples or

additional noise.

Preventing Bus Traffic Errors

The ADXL375 CS pin is used both for initiating SPI transactions

and for enabling I2C mode. When the ADXL375 is used on a SPI

bus with multiple devices, its CS pin is held high while the master

communicates with the other devices. There may be conditions

where a SPI command transmitted to another device looks like

a valid I2C command. In this case, the ADXL375 interprets this

command as an attempt to communicate in I2C mode and may

interfere with other bus traffic. Unless bus traffic can be ade-

quately controlled to ensure that such a condition never occurs,

it is recommended that a logic gate be added in front of Pin 13

(SDA/SDI/SDIO), as shown in Figure 24. This OR gate holds the

SDA line high when CS is high to prevent SPI bus traffic at the

ADXL375 from appearing as an I2C start command.

PROCESSOR

D OUT

D IN/OUT

D IN

D OUT

ADXL375

SDA/SDI/SDIO

SDO

SCLK

Figure 24. Recommended SPI Connection Diagram

When Using Multiple SPI Devices on a Single Bus

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