SIC401DB datasheet(15/28 Pages) VISHAY

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Vishay Siliconix

SiC401A, SiC401BCD

Document Number: 63835

S12-2109-Rev. C, 03-Sep-12

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: powerictechsupport@vishay.com

This method automatically produces an on-time that is

proportional to VOUT and inversely proportional to VIN. Under

steady-state conditions, the switching frequency can be

determined from the on-time by the following equation.

The SiC401A/B uses an external resistor to set the ontime

which indirectly sets the frequency. The on-time can be

programmed to provide operating frequency up to 1 MHz

using a resistor between the tON pin and ground. The resistor

value is selected by the following equation.

The constant, k, equals 1, when VDD is greater than 3.6 V. If

VDD is less than 3.6 V and VIN is greater than (VDD -1.75) x 10,

k is shown by the following equation.

The maximum RTON value allowed is shown by the following

equation.

VOUT Voltage Selection

The switcher output voltage is regulated by comparing VOUT

as seen through a resistor divider at the FB pin to the internal

600 mV reference voltage, see figure 3.

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage VOUT is offset by the output ripple according to the

following equation.

When a large capacitor is placed in parallel with R1 (CTOP)

VOUT is shown by the following equation.

Enable and Power-Save Inputs

The EN/PSV input is used to enable or disable the switching

regulator. When EN/PSV is low (grounded), the switching

regulator is off and in its lowest power state. When off, the

output of the switching regulator soft-discharges the output

into a 15

 internal resistor via the V

OUT pin. When EN/PSV

is allowed to float, the pin voltage will float to 33 % of the

voltage at VDD. The switching regulator turns on with

power-save disabled and all switching is in forced continuous

mode.

When EN/PSV is high (above 44 % of the voltage at VDD),

the switching regulator turns on with power-save enabled.

The SiC401A/B P-Save operation reduces the switching

frequency according to the load for increased efficiency at

light load conditions.

Forced Continuous Mode Operation

The SiC401A/B operates the switcher in FCM (Forced

Continuous Mode) by floating the EN/PSV pin (see figure 4).

In this mode one of the power MOSFETs is always on, with

no intentional dead time other than to avoid cross-

conduction. This feature results in uniform frequency across

the full load range with the trade-off being poor efficiency at

light loads due to the high-frequency switching of the

MOSFETs. DH is gate signal to drive upper MOSFET. DL is

lower gate signal to drive lower MOSFET

Figure 2 - On-Time Generation

Figure 3 - Output Voltage Selection

VREF

VOUT

VIN

Rton

On-time = K x Rton x (VOUT/VIN)

FB comparator

One-shot

timer

Gate

drives

ESR

VOUT

COUT

VLX

fSW =

VOUT

tON x VIN

Rton =

25 pF x fSW

(VDD - 1.75) x 10

k =

Rton_MAX =

VIN_MIN

15 µA

VOUT

To FB pin

VOUT = 0.6 x 1 +

VRIPPLE

VOUT = 0.6 x 1 +

VRIPPLE

R2 x R1

R2 + R1

ωCTOP

1 +

1 + (R1ωCTOP)

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