SIC401DB datasheet(22/28 Pages) VISHAY

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Document Number: 63835

S12-2109-Rev. C, 03-Sep-12

Vishay Siliconix

SiC401A, SiC401BCD

www.vishay.com

Document Number: 63835

S12-2109-Rev. C, 03-Sep-12

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: powerictechsupport@vishay.com

Using Ceramic Output Capacitors

When the system is using high ESR value capacitors, the

feedback voltage ripple lags the phase node voltage by 90°.

Therefore, the converter is easily stabilized. When the

system is using ceramic output capacitors, the ESR value is

normally too small to meet the above ESR criteria. As a

result, the feedback voltage ripple is 180° from the phase

node and behaves in an unstable manner. In this application

it is necessary to add a small virtual ESR network that is

composed of two capacitors and one resistor, as shown in

figure 14.

The ripple voltage at FB is a superposition of two voltage

sources: the voltage across CL and output ripple voltage.

They are defined in the following equations.

Figure 15 shows the magnitude of the ripple contribution due

to CL at the FB pin.

It is shown by the following equation.

Figure 16 shows the magnitude of the ripple contribution due

to the output voltage ripple at the FB pin.

It is shown by the following equation.

The purpose of this network is to couple the inductor current

ripple information into the feedback voltage such that the

feedback voltage has 90° phase lag to the switching node

similar to the case of using standard high ESR capacitors.

This is illustrated in figure 17.

The magnitude of the feedback ripple voltage, which is

dominated by the contribution from CL, is controlled by the

value of R1, R2 and CC. If the corner frequency of (R1//R2) x

CC is too high, the ripple magnitude at the FB pin will be

smaller, which can lead to double-pulsing. Conversely, if the

corner frequency of (R1//R2) x CC is too low, the ripple

magnitude at FB pin will be higher. Since the SiC401A/B

regulates to the valley of the ripple voltage at the FB pin, a

high ripple magnitude is undesirable as it significantly

impacts the output voltage regulation. As a result, it is

desirable to select a corner frequency for (R1//R2) x CC to

achieve enough, but not excessive, ripple magnitude and

phase margin. The component values for R1, R2, and CC

should be calculated using the following procedure.

Select CL (typical 10 nF) and RL to match with L and DCR

time constant using the following equation.

Figure 14 - Virtual ESR Ramp Current

Figure 15 - FB Voltage by CL Voltage

CL =

IL x DCR (s x L/DCR + 1)

S x RL x CL + 1

ΔV

OUT =

ΔIL

8C x fSW

VFB

CL = VCL x

(R1//R2) x S x CC

(R1//R2) x S x CC + 1

Figure 16 - FB Voltage by Output Voltage

Figure 17 - FB Voltage in Phasor Diagram

VFB

ΔV

OUT = ΔVOUT x

R1//

+ R2

S x CC

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