SIC401DB datasheet(19/28 Pages) VISHAY

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Vishay Siliconix

SiC401A, SiC401BCD

Document Number: 63835

S12-2109-Rev. C, 03-Sep-12

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: powerictechsupport@vishay.com

feature can be used to prevent false UV faults for the PWM

output by programming with a resistor divider at the VIN, ENL

and AGND pins. When SiC401A/B has an external bias

voltage at VDD and the ENL pin is used to program the VIN

UVLO feature, the voltage at FBL needs to be higher than

750 mV to force the LDO off.

Timing is important when driving ENL with logic and not

implementing VIN UVLO. The ENL pin must transition from

high to low within 2 switching cycles to avoid the PWM output

turning off. If ENL goes below the VIN UVLO threshold and

stays above 1 V, then the switcher will turn off but the LDO

will remain on.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

1. ENL pin

2. VLDO output

When the ENL pin is high and VIN is above the UVLO point,

the LDO will begin start-up. During the initial phase, when the

VDD voltage (which is the LDO output voltage) is less than

0.75 V, the LDO initiates a current-limited start-up (typically

65 mA) to charge the output capacitors while protecting from

a short circuit event. When VDD is greater than 0.75 V but still

less than 90 % of its final value (as sensed at the FBL pin),

the LDO current limit is increased to ~115 mA. When VDD

has reached 90 % of the final value (as sensed at the FBL

pin), the LDO current limit is increased to ~ 200 mA and the

LDO output is quickly driven to the nominal value by the

internal LDO regulator. It is recommended that during LDO

start-up to hold the PWM switching off until the LDO has

reached 90 % of the final value. This prevents overloading

the current-limited LDO output during the LDO start-up.

Due to the initial current limitations on the LDO during power

up (figure 11), any external load attached to the VDD pin must

be limited to less than the start up current before the LDO

has reached 90 % of its final regulation value.

LDO Switch-Over Poeration

The SiC401A/B includes a switch-over function for the LDO.

The switch-over function is designed to increase efficiency

by using the more efficient DC/DC converter to power the

LDO output, avoiding the less efficient LDO regulator when

possible. The switch-over function connects the VDD pin

directly to the VOUT pin using an internal switch. When the

switch-over is complete the LDO is turned off, which results

in a power savings and maximizes efficiency. If the LDO

output is used to bias the SiC401A/B, then after switch-over

the device is self-powered from the switching regulator with

the LDO turned off.

The switch-over starts 32 switching cycles after PGOOD

output goes high. The voltages at the VDD and VOUT pins are

then compared; if the two voltages are within ± 300 mV of

each other, the VDD pin connects to the VOUT pin using an

internal switch, and the LDO is turned off. To avoid unwanted

switch-over, the minimum difference between the voltages

for VOUT and VDD should be ± 500 mV.

It is not recommended to use the switch-over feature for an

output voltage less than VDD UVLO threshold since the

SiC401A/B is not operational below that threshold.

Switch-Over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that are

inherent to its construction, as shown in figure 12. If the

voltage at the VOUT pin is higher than VDD, then the

respective diode will turn on and the current will flow through

this diode. This has the potential of damaging the device.

Therefore, VOUT must be less than VDD to prevent damaging

the device.

Design Procedure

When designing a switch mode supply the input voltage

range, load current, switching frequency, and inductor ripple

current must be specified.

The maximum input voltage (VIN max.) is the highest specified

input voltage. The minimum input voltage (VIN min.) is

determined by the lowest input voltage after evaluating the

voltage drops due to connectors, fuses, switches, and PCB

traces.

The following parameters define the design:

• Nominal output voltage (VOUT)

• Static or DC output tolerance

• Transient response

• Maximum load current (IOUT)

There are two values of load current to evaluate - continuous

load current and peak load current. Continuous load current

relates to thermal stresses which drive the selection of

the inductor and input capacitors. Peak load current

determines instantaneous component stresses and filtering

requirements such as inductor saturation, output capacitors,

and design of the current limit circuit.

The following values are used in this design:

• VIN = 12 V ± 10 %

Figure 11 - LDO Start-Up

Figure 12 - Switch-over MOSFET Parasitic Diodes

VOUT

LDO

Parastic diode

Switchover

MOSFET

Switchover

control

VDD

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