ADSP-21486KSWZ-2AB datasheet(33/68 Pages) AD

33 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 33 of 68

March 2013

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Read

Parameter

Min

Max

Unit

Timing Requirements

tDAD

1, 2, 3

Address Selects Delay to Data Valid

W + tSDCLK –5.4

tDRLD

1, 3

AMI_RD Low to Data Valid

W – 3.2

tSDS

Data Setup to AMI_RD High

2.5

tHDRH

4, 5

Data Hold from AMI_RD High

tDAAK

2, 6

AMI_ACK Delay from Address, Selects

tSDCLK –9.5 + W

tDSAK

AMI_ACK Delay from AMI_RD Low

W – 7

Switching Characteristics

tDRHA

Address Selects Hold After AMI_RD High

RHC + 0.20

tDARL

Address Selects to AMI_RD Low

tSDCLK – 3.8

tRW

AMI_RD Pulse Width

W – 1.4

tRWR

AMI_RD High to AMI_RD Low

HI + tSDCLK – 1

W = (number of wait states specified in AMICTLx register) × tSDCLK.

RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK

Where PREDIS = 0

HI = RHC: Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank

HI = RHC + (3 × tSDCLK): Read to Read from same bank

HI = RHC + Max (IC, (3 × tSDCLK): Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × tSDCLK

H = (number of hold cycles specified in AMICTLx register) × tSDCLK

1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS.

2 The falling edge of MSx, is referenced.

3 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not

used.

4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads.

6 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).

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