ADSP-21486KSWZ-2AB datasheet(23/68 Pages) AD

23 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 23 of 68

March 2013

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 18. All

of the timing specifications for the ADSP-2148x peripherals are

defined in relation to tPCLK. See the peripheral specific section

for each peripheral’s timing information.

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-214xx SHARC Processor Hard-

ware Reference.

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 19. While no specific power-up sequencing is required

between VDD_EXT and VDD_INT, there are some considerations

that system designs should take into account.

• No power supply should be powered up for an extended

period of time (> 200 ms) before another supply starts to

ramp up.

•If the VDD_INT power supply comes up after VDD_EXT, any

pin, such as RESETOUT and RESET, may actually drive

momentarily until the VDD_INT rail has powered up.

Systems sharing these signals on the board must determine

if there are any issues that need to be addressed based on

this behavior.

Note that during power-up, when the VDD_INT power supply

comes up after VDD_EXT, a leakage current of the order of three-

state leakage current pull-up, pull-down may be observed on

any pin, even if that is an input only (for example the RESET

pin) until the VDD_INT rail has powered up.

Table 18. Clock Periods

Timing

Requirements

Description

tCK

CLKIN Clock Period

tCCLK

Processor Core Clock Period

tPCLK

Peripheral Clock Period = 2 × tCCLK

tSDCLK

SDRAM Clock Period = (tCCLK) × SDCKR

Table 19. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

tRSTVDD

RESET Low Before VDD_EXT or VDD_INT On

tIVDDEVDD

VDD_INT On Before VDD_EXT

–200

+200

tCLKVDD

CLKIN Valid After VDD_INT and VDD_EXT Valid

200

tCLKRST

CLKIN Valid Before RESET Deasserted

102

μs

tPLLRST

PLL Control Setup Before RESET Deasserted

203

μs

Switching Characteristic

tCORERST

4, 5

Core Reset Deasserted After RESET Deasserted

4096 × tCK + 2 × tCCLK

1 Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Based on CLKIN cycles.

4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

5 The 4096 cycle count depends on tSRST specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

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