ADSP-21486KSWZ-2AB datasheet(16/68 Pages) AD

16 / 68 page

Rev. B

Page 16 of 68

March 2013

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

MLBCLK1

Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-

nized to the MOST network and provides the timing for the entire MLB interface at

49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be

grounded.

MLBDAT1

I/O/T in 3

pin mode. I

in 5 pin

mode.

High-Z

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and

is received by all other MLB devices including the MLB controller. The MLBDAT line

carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB

controller is not used, this pin should be grounded.

MLBSIG1

I/O/T in 3

pin mode. I

in 5 pin

mode

High-Z

Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address

generated by the MLB Controller, as well as the Command and RxStatus bytes from

MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,

this pin should be grounded.

MLBDO1

O/T

High-Z

Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.

This serves as the output data pin in 5-pin mode. When the MLB controller is not used,

this pin should be connected to ground.

MLBSO1

O/T

High-Z

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is

not used, this pin should be connected to ground.

TDI

I (ipu)

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

TDO

O/T

High-Z

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS

I (ipu)

Test Mode Select (JTAG). Used to control the test state machine.

TCK

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST

I (ipu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor.

EMU

O (O/D, ipu)

High-Z

Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools

product line of JTAG emulators target board connector only.

Table 11. Pin Descriptions (Continued)

Name

Type

State

During/

After Reset

Description

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

ADSP-21486KSWZ-2AB Datasheet(PDF) 16 Page - Analog Devices

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