ADSP-21486KSWZ-2AB datasheet(47/68 Pages) AD

47 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 47 of 68

March 2013

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 47. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 47. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

tSISFS

Frame Sync Setup Before Serial Clock Rising Edge

tSIHFS

Frame Sync Hold After Serial Clock Rising Edge

tSISD

Data Setup Before Serial Clock Rising Edge

tSIHD

Data Hold After Serial Clock Rising Edge

tSITXCLKW

Transmit Clock Width

tSITXCLK

Transmit Clock Period

tSISCLKW

Clock Width

tSISCLK

Clock Period

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Figure 33. S/PDIF Transmitter Input Timing

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSITXCLKW

tSITXCLK

tSISCLKW

tSISCLK

tSISFS

tSIHFS

tSISD

tSIHD

Table 48. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Max

Unit

Frequency for TxCLK = 384 × Frame Sync

Oversampling Ratio × Frame Sync <= 1/tSITXCLK MHz

Frequency for TxCLK = 256 × Frame Sync

49.2

MHz

Frame Rate (FS)

192.0

kHz

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