ADSP-21486KSWZ-2AB datasheet(42/68 Pages) AD

42 / 68 page

Rev. B

Page 42 of 68

March 2013

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 40. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

PDAP chapter of the ADSP-214xx SHARC Processor Hardware

Reference. Note that the 20 bits of external PDAP data can be

provided through the ADDR23–4 pins or over the DAI pins.

Table 40. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

tSPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

2.5

tHPHOLD

PDAP_HOLD Hold After PDAP_CLK Sample Edge

2.5

tPDSD

PDAP_DAT Setup Before PDAP_CLK Sample Edge

3.85

tPDHD

PDAP_DAT Hold After PDAP_CLK Sample Edge

2.5

tPDCLKW

Clock Width

(tPCLK × 4) ÷ 2 – 3

tPDCLK

Clock Period

tPCLK × 4

Switching Characteristics

tPDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

2 × tPCLK + 3

tPDSTRB

PDAP Strobe Pulse Width

2 × tPCLK – 1.5

1 Source pins of PDAP_DATA are ADDR23–4 or DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are 1) DAI pins; 2) CLKIN through PCG; 3) DAI pins through

PCG; or 4) ADDR3–2 pins.

Figure 26. PDAP Timing

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_HOLD)

DAI_P20–1

(PDAP_STROBE)

tPDSTRB

tPDHLDD

tPDHD

tPDSD

tSPHOLD

tHPHOLD

tPDCLK

tPDCLKW

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

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