ADSP-21486KSWZ-2AB datasheet(35/68 Pages) AD

35 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 35 of 68

March 2013

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 33. AMI Write

Parameter

Min

Max

Unit

Timing Requirements

tDAAK

1, 2

AMI_ACK Delay from Address, Selects

tSDCLK – 9.7 + W

tDSAK

1, 3

AMI_ACK Delay from AMI_WR Low

W – 6

Switching Characteristics

tDAWH

Address Selects to AMI_WR Deasserted

tSDCLK –3.1+ W

tDAWL

Address Selects to AMI_WR Low

tSDCLK –3

tWW

AMI_WR Pulse Width

W – 1.3

tDDWH

Data Setup Before AMI_WR High

tSDCLK –3.7+ W

tDWHA

Address Hold After AMI_WR Deasserted

H + 0.15

tDWHD

Data Hold After AMI_WR Deasserted

tDATRWH

Data Disable After AMI_WR Deasserted

tSDCLK – 4.3 + H

tSDCLK + 4.9 + H

tWWR

AMI_WR High to AMI_WR Low

tSDCLK –1.5+ H

tDDWR

Data Disable Before AMI_RD Low

2 × tSDCLK – 6

tWDE

AMI_WR Low to Data Enabled

tSDCLK – 3.7

W = (number of wait states specified in AMICTLx register) × tSDCLK

H = (number of hold cycles specified in AMICTLx register) × tSDCLK

1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).

2 The falling edge of MSx is referenced.

3 Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

4 See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads.

5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks.

Figure 20. AMI Write

AMI_ACK

AMI_DATA

tDAWH

tDWHA

tWWR

tDATRWH

tDWHD

tWW

tDDWR

tDDWH

tDAWL

tWDE

tDSAK

tDAAK

AMI_RD

AMI_WR

AMI_ADDR

AMI_MSx

ADSP-21486KSWZ-2AB Datasheet(PDF) 35 Page - Analog Devices

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