ADSP-21486KSWZ-2AB datasheet(15/68 Pages) AD

15 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 15 of 68

March 2013

SDRAS

O/T (ipu)

High-Z/

driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS

O/T (ipu)

High-Z/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDWE

O/T (ipu)

High-Z/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCKE

O/T (ipu)

High-Z/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10

O/T (ipu)

High-Z/

driven high

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM

accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.

SDDQM

O/T (ipu)

High-Z/

driven high

DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal

for read accesses. Input data is masked when DQM is sampled high during a write cycle.

The SDRAM output buffers are placed in a High-Z state when DQM is sampled high

during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-

ization completes. Afterwards it is driven low irrespective of whether any SDRAM

accesses occur or not.

SDCLK

O/T (ipd)

High-Z/

driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See

Figure 41 on Page 55. For models in the 100-lead package, the SDRAM interface should

be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL

DAI _P20–1

I/O/T (ipu)

High-Z

Digital Applications Interface. These pins provide the physical interface to the DAI

SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.

The configuration registers of these peripherals then determines the exact behavior of

the pin. Any input or output signal present in the DAI SRU may be routed to any of these

pins.

DPI _P14–1

I/O/T (ipu)

High-Z

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral

inputs or outputs connected to the pin and to the pin’s output enable. The configu-

ration registers of these peripherals then determines the exact behavior of the pin. Any

input or output signal present in the DPI SRU may be routed to any of these pins.

WDT_CLKIN

Watchdog Timer Clock Input. This pin should be pulled low when not used.

WDT_CLKO

Watchdog Resonator Pad Output.

WDTRSTO

O (ipu)

Watchdog Timer Reset Out.

THD_P

Thermal Diode Anode. When not used, this pin can be left floating.

THD_M

Thermal Diode Cathode. When not used, this pin can be left floating.

Table 11. Pin Descriptions (Continued)

Name

Type

State

During/

After Reset

Description

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

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