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EP3SL70 Datasheet(PDF) 128 Page - Altera Corporation |
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EP3SL70 Datasheet(HTML) 128 Page - Altera Corporation |
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128 / 341 page  1–118 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Table 1–69 and Table 1–70 list the EP3SL110 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1–69 lists the EP3SL110 column pin delay adders when using the regional clock. DIFFERENTIAL 1.8-V SSTL CLASS I 8mA GCLK tco 3.125 3.370 4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898 ns GCLK PLL t co 1.345 1.531 1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318 ns DIFFERENTIAL 1.8-V SSTL CLASS I 10mA GCLK tco 3.105 3.350 4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874 ns GCLK PLL t co 1.325 1.511 1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294 ns DIFFERENTIAL 1.8-V SSTL CLASS I 12mA GCLK t co 3.102 3.346 4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871 ns GCLK PLL t co 1.322 1.507 1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291 ns DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK t co 3.107 3.350 4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855 ns GCLK PLL t co 1.327 1.511 1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275 ns DIFFERENTIAL 1.8-V SSTL CLASS II 16mA GCLK t co 3.100 3.343 4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860 ns GCLK PLL t co 1.320 1.504 1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280 ns DIFFERENTIAL 2.5-V SSTL CLASS I 8mA GCLK t co 3.138 3.382 4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895 ns GCLK PLL tco 1.358 1.543 1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315 ns DIFFERENTIAL 2.5-V SSTL CLASS I 12mA GCLK t co 3.120 3.365 4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880 ns GCLK PLL tco 1.340 1.526 1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300 ns DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK t co 3.106 3.349 4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855 ns GCLK PLL t co 1.326 1.510 1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275 ns Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–69. EP3SL110 Column Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.186 0.171 0.245 0.255 0.268 0.261 0.393 0.248 0.277 0.267 0.364 ns RCLK PLL input adder 2.391 2.371 3.577 4.036 4.418 4.225 4.574 4.044 4.442 4.246 4.635 ns RCLK output adder -0.374 -0.162 -0.226 -0.233 -0.244 -0.239 -0.367 -0.111 -0.123 -0.116 -0.296 ns RCLK PLL output adder -2.001 -1.786 -2.669 -2.844 -2.996 -2.879 -2.722 -2.699 -3.067 -2.798 -2.773 ns |
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