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EP3SL70 Datasheet(PDF) 156 Page - Altera Corporation |
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EP3SL70 Datasheet(HTML) 156 Page - Altera Corporation |
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156 / 341 page ![]() 1–146 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Table 1–79 and Table 1–80 list the EP3SL150 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1–79 lists the EP3SL150 column pin delay adders when using the regional clock. Table 1–80 lists the EP3SL150 row pin delay adders when using the regional clock. EP3SL200 I/O Timing Parameters Table 1–81 through Table 1–84 list the maximum I/O timing parameters for EP3SL200 devices for single-ended I/O standards. Table 1–81 lists the EP3SL200 column pins input timing parameters for single-ended I/O standards. Table 1–79. EP3SL150 Column Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.198 0.152 0.22 0.258 0.27 0.262 0.393 0.244 0.271 0.261 0.495 ns RCLK PLL input adder 2.453 2.426 3.654 4.098 4.422 4.224 4.664 4.106 4.447 4.101 4.707 ns RCLK output adder -0.374 -0.152 -0.216 -0.232 -0.248 -0.227 -0.367 -0.11 -0.127 -0.106 -0.303 ns RCLK PLL output adder -2.017 -1.798 -2.68 -2.859 -3.011 -2.872 -2.715 -2.714 -3.082 -2.791 -2.766 ns Table 1–80. EP3SL150 Row Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.107 0.115 0.164 0.165 0.167 0.165 0.285 0.158 0.159 0.158 0.29 ns RCLK PLL input adder 0.074 0.075 0.116 0.123 0.129 0.126 0.218 0.114 0.118 0.114 0.223 ns RCLK output adder -0.093 -0.103 -0.137 -0.136 -0.133 -0.134 -0.257 -0.125 -0.121 -0.122 -0.261 ns RCLK PLL output adder -0.063 -0.065 -0.097 -0.102 -0.103 -0.102 -0.198 -0.088 -0.089 -0.088 -0.202 ns Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V 3.3-V LVTTL GCLK t su -1.137 -1.173 -1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002 -1.934 -2.482 ns t h 1.285 1.319 2.032 2.008 2.259 2.177 2.724 2.008 2.259 2.177 2.724 ns GCLK PLL t su -1.465 -1.465 -2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558 -2.477 -2.997 ns t h 1.778 1.778 2.727 2.776 3.113 3.000 3.543 2.776 3.113 3.000 3.543 ns 3.3-V LVCMOS GCLK t su -1.137 -1.173 -1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002 -1.934 -2.482 ns t h 1.285 1.319 2.032 2.008 2.259 2.177 2.724 2.008 2.259 2.177 2.724 ns GCLK PLL t su -1.465 -1.465 -2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558 -2.477 -2.997 ns t h 1.778 1.778 2.727 2.776 3.113 3.000 3.543 2.776 3.113 3.000 3.543 ns |
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