ADAS1000 datasheet(71/80 Pages) AD

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Data Sheet

ADAS1000/ADAS1000-1/ADAS1000-2

Rev. A | Page 71 of 80

Table 52. Frame Header (FRAMES) Address 0x40, Reset Value = 0x8000001

R/W

Default

Bit

Name

Function

Marker

Header marker, set to 1 for the header.

Ready bit

Ready bit indicates if ECG frame data is calculated and ready for reading.

0 = ready, data frame follows.

1 = busy.

[29:28]

Overflow [1:0]

Overflow bits indicate that since the last frame read, a number of frames have

been missed. This field saturates at the maximum count. The data in the frame

including this header word is valid but old if the overflow bits are >0.

When using skip mode (FRMCTL register (0x0A), Bits[3:2]), the overflow bit acts as a

flag, where a nonzero value indicates an overflow.

00 = 0 missed.

01 = 1 frame missed.

10 = 2 frames missed.

11 = 3 or more frames missed.

Fault

Internal device error detected.

0 = normal operation.

1 = error condition.

Pace 3 detected

Pace 3 indicates pacing artifact was qualified at most recent point.

0 = no pacing artifact.

1 = pacing artifact present.

Pace 2 detected

Pace 2 indicates pacing artifact was qualified at most recent point.

0 = no pacing artifact.

1 = pacing artifact present.

Pace 1 detected

Pace 1 indicates pacing artifact was qualified at most recent point.

0 = no pacing artifact.

1 = pacing artifact present.

Respiration

0 = no new respiration data.

1 = respiration data updated.

Lead-off detected

If both dc and ac lead-off are enabled, this bit is the OR of all the ac lead-off detect

flags. If only ac or dc lead-off is enabled, this bit reflects the OR of all dc and ac

lead-off flags.

0 = all leads connected.

1 = one or more lead-off detected.

DC lead-off detected

0 = all leads connected.

1 = one or more lead-off detected.

ADC out of range

0 = ADC within range.

1 = ADC out of range.

[19:0]

Reserved

If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.

Table 53. Frame CRC Register (CRC) Address 0x41, Reset Value = 0xFFFFFF1

R/W

Bit

Name

Function

[23:0]

CRC

Cyclic redundancy check

The CRC register is a 32-bit word for 2 kHz and 16 kHz data rate and a 16-bit word for 128 kHz rate. See Table 22 for more details.

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