AT90USB646 datasheet(302/456 Pages) ATMEL

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302

7593L–AVR–09/12

AT90USB64/128

• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error

Set by hardware when a STALL handshake has been received on the current bank of the Pipe.

The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI-

ENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

For Isochronous Pipe:

Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-

rupt if the TXSTPE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 0 - RXINI - IN Data received

Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-

gers an interrupt if the RXINE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 7 - FLERRE - Flow Error Interrupt enable

Set to enable the OVERFI and UNDERFI interrupts.

Clear to disable the OVERFI and UNDERFI interrupts.

• 6 - NAKEDE -NAK Handshake Received Interrupt Enable

Set to enable the NAKEDI interrupt.

Clear to disable the NAKEDI interrupt.

• 5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4 - PERRE -PIPE Error Interrupt Enable

Set to enable the PERRI interrupt.

Clear to disable the PERRI interrupt.

• 3 - TXSTPE - SETUP Bank ready Interrupt Enable

Set to enable the TXSTPI interrupt.

Clear to disable the TXSTPI interrupt.

• 2 - TXOUTE - OUT Bank ready Interrupt Enable

Set to enable the TXOUTI interrupt.

Clear to disable the TXOUTI interrupt.

• 1 - RXSTALLE - STALL Received Interrupt Enable

Set to enable the RXSTALLI interrupt.

Clear to disable the RXSTALLI interrupt.

Bit

FLERRE

NAKEDE

PERRE

TXSTPE

TXOUTE

RXSTALLE

RXINE

UPIENX

Read/write

Initial value

AT90USB646 Datasheet(PDF) 302 Page - ATMEL Corporation

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