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AT90USB646 Datasheet(PDF) 303 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 303 Page - ATMEL Corporation |
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303 / 456 page  303 7593L–AVR–09/12 AT90USB64/128 • 0 - RXINE - IN Data received Interrupt Enable Set to enable the RXINI interrupt. Clear to disable the RXINI interrupt. • 7-0 - PDAT7:0 - Pipe Data bits Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM. • 7-3 - Reserved The value read from these bits is always 0. Do not set these bits. • 2-0 - PBYCT10:8 - Byte count (high) bits Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is provided by the UPBCLX register. • 7-0 - PBYCT7:0 - Byte Count (low) bits Set by the hardware. PBYCT10:0 is: - (for OUT Pipe) increased after each writing into the Pipe and decremented after each byte sent, - (for IN Pipe) increased after each byte received by the host, and decremented after each byte read by the software. • 7 - Reserved The value read from these bits is always 0. Do not set these bits. • 6-0 - PINT6:0 - Pipe Interrupts bits Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding endpoint interrupt enable bit is set. Cleared by hardware when the interrupt source is served. Bit 7 654 321 0 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 UPDATX Read/write RW RW RW RW RW RW RW RW Initial value 0 000 000 0 Bit 7 65 43 2 1 0 - - - - - PBYCT10 PBYCT9 PBYCT8 UPBCHX Read/write RRR Initial value 00 00 0 0 0 0 Bit 7 65432 10 PBYCT7 PBYCT6 PBYCT5 PBYCT4 PBYCT3 PBYCT2 PBYCT1 PBYCT0 UPBCLX Read/write RR RRRRRR Initial value 0 00000 00 Bit 7 65432 10 - PINT6 PINT5 PINT4 PINT3 PINT2 PINT1 PINT0 UPINT Read/write Initial value 0 00000 00 |
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