S25FS-S datasheet(105/154 Pages) SPANSION

105 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

105

Da ta

Shee t

(Prelim i nar y )

in Configuration Register 2 to 0. In the FS128S, higher order address bits above A23 in the 4 byte address

commands, or commands using 4-byte address mode are not relevant and are ignored because the flash

array is only 128 Mbits in size.

The Quad I/O and QPI commands provide a performance improvement option controlled by mode bits that

are sent following the address bits. The mode bits indicate whether the command following the end of the

current read will be another read of the same type, without an instruction at the beginning of the read. These

mode bits give the option to eliminate the instruction cycles when doing a series of Quad Read accesses.

Some commands require delay cycles following the address or mode bits to allow time to access the memory

array - read latency. The delay or read latency cycles are traditionally called dummy cycles. The dummy

cycles are ignored by the memory thus any data provided by the host during these cycles is “don’t care” and

the host may also leave the SI signal at high impedance during the dummy cycles. When MIO commands are

used the host must stop driving the IO signals (outputs are high impedance) before the end of last dummy

cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The

number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration

falling edge. SPI outputs are traditionally driven to a new value on the falling edge of each SCK. Zero dummy

cycles means the returning data is driven by the memory on the same falling edge of SCK that the host stops

driving address or mode bits.

The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on

all data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host

memory controller determine the phase shift from SCK to data edges so that the memory controller can

capture data at the center of the data eye.

When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides one or more

dummy cycles should be selected to allow additional time for the host to stop driving before the memory starts

driving data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC

that provides five or more dummy cycles should be selected to allow one cycle of additional time for the host

to stop driving before the memory starts driving the 4-cycle DLP.

Each read command ends when CS# is returned High at any point during data return. CS# must not be

returned High during the mode or dummy cycles before data returns as this may cause mode bits to be

captured incorrectly; making it indeterminate as to whether the device remains in Continuous Read mode.

10.4.1

Read (Read 03h or 4READ 13h)

The instruction

 03h (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or

 03h (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or

 13h is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock

frequency for the Read command is 50 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to

the next higher address in sequential order after each byte of data is shifted out. The entire memory can

therefore be read out with one single read instruction and address 000000h provided. When the highest

address is reached, the address counter will wrap around and roll back to 000000h, allowing the read

sequence to be continued indefinitely.

Figure 10.27 Read Command Sequence (3-Byte Address, 03h or 13h)

Note:

1. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 13h.

CS#

SCK

Phase

Instruction

Address

Data1

DataN

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