AM79C972BVCW datasheet(24/130 Pages) AMD

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Am79C972

SRD

Serial Receive Data

Input/Output

SRD is the decoded NRZ data from the network when

in GPSI mode. This signal can be used for external ad-

dress detection.

Note: When the MII port is selected, SRD will not gen-

erate transitions and receive data must be derived from

the Media Independent Interface RXD[3:0] pins.

Note also that the SRD pin is multiplexed with the

MIIRXFRTGD, EEDO, and LED3 pins.

SRDCLK

Serial Receive Data Clock

Output

Serial Receive Data is synchronous with reference to

SRDCLK.

Note: When the MII port is selected, SRDCLK will not

generate transitions and the receive clock must be de-

rived from the MII RX_CLK pin.

Note also that the SRDCLK pin is multiplexed with the

MIIRXFRTGE and LED2 pins.

RXFRTGD

Receive Frame Tag Data

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is not selected, the RXFRTGD pin

becomes a data input pin for the Receive Frame Tag.

See the Receive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the

RXD[0] pin.

RXFRTGE

Receive Frame Tag Enable

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is not selected, the RXFRTGE pin

becomes a data input enable pin for the Receive Frame

Tag. See the Receive Frame Tagging section for de-

tails.

Note: The RXFRTGE pin is multiplexed with the

RX_DV pin.

MIIRXFRTGD

MII Receive Frame Tag Enable

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is selected, the MIIRXFRTGD pin

becomes a data input pin for the Receive Frame Tag.

See the Receive Frame Tagging section for details.

Note: The MIIRXFRTGD pin is multiplexed with the

SRD, EEDO, and LED3 pins.

MIIRXFRTGE

MII Receive Frame Tag Enable

Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII is selected, the MIIRXFRTGE pin

becomes a data input enable pin for the Receive Frame

Tag. See the Receive Frame Tagging section for de-

tails.

Note: The MIIRXFRTGE pin is multiplexed with the

SRDCLK and LED2 pins.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull up resistor.

TDI

Test Data In

Input

TDI is the test data input path to the Am79C972 con-

troller. The pin has an internal pull up resistor.

TDO

Test Data Out

Output

TDO is the test data output path from the Am79C972

controller. The pin is tri-stated when the JTAG port is in-

active.

TMS

Test Mode Select

Input

A serial input bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull up resistor.

AM79C972BVCW Datasheet(PDF) 24 Page - Advanced Micro Devices

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