AM79C972BVCW datasheet(28/130 Pages) AMD

28 / 130 page

Am79C972

Figure 1. Slave Configuration Read

The Am79C972 controller will not assert DEVSEL if it

detects an address match, but the PCI command is not

of the correct type. In memory mapped I/O mode, the

Am79C972 controller aliases all accesses to the I/O re-

sources of the command types Memory Read Multiple

and Memory Read Line to the basic Memory Read com-

mand. All accesses of the type Memory Write and In-

validate are aliased to the basic Memory Write

command. Eight-bit, 16-bit, and 32-bit non-burst trans-

actions are supported. The Am79C972 controller de-

codes all 32 address lines to determine which I/O

resource is accessed.

The typical number of wait states added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C972 controller is six to seven clock cycles,

depending upon the relative phases of the internal Buff-

er Management Unit clock and the CLK signal, since

the internal Buffer Management Unit clock is a divide-

by-two version of the CLK signal.

The Am79C972 controller does not support burst trans-

fers for access to its I/O resources. When the host keeps

FRAME asserted for a second data phase, the

Am79C972 controller will disconnect the transfer.

Figure 2. Slave Configuration Write

The Am79C972 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C972 controller

is capable of detecting an I/O or a memory-mapped

I/O cycle even when its address phase immediately fol-

lows the data phase of a transaction to a different target,

without any idle state in-between. There will be no con-

tention on the DEVSEL, TRDY, and STOP signals, since

the Am79C972 controller asserts DEVSEL on the sec-

ond clock after FRAME is asserted (medium timing) See

Figure 3 and Figure 4.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

23456

1010

PAR

DEVSEL is sampled

DATA

ADDR

21485C-4

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

23456

1011

PAR

DATA

ADDR

21485C-5

AM79C972BVCW Datasheet(PDF) 28 Page - Advanced Micro Devices

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