AM79C972BVCW datasheet(92/130 Pages) AMD

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Am79C972

Table 16.

PCI Configuration Space Layout

The Am79C972 controller supports mapping the ad-

dress space to both I/O and memory space. The value

in the PCI I/O Base Address register determines the

start address of the I/O address space. The register is

typically programmed by the PCI configuration utility

after system power-up. The PCI configuration utility

must also set the IOEN bit in the PCI Command register

to enable I/O accesses to the Am79C972 controller. For

memory mapped I/O access, the PCI Memory Mapped

I/O Base Address register controls the start address of

the memory space. The MEMEN bit in the PCI Com-

mand register must also be set to enable the mode. Both

base address registers can be active at the same time.

The Am79C972 controller supports two modes for ac-

cessing the I/O resources. For backwards compatibility

with AMD’s 16-bit Ethernet controllers, Word I/O is the

default mode after power up. The device can be config-

ured to DWord I/O mode by software.

I/O Registers

The Am79C972 controller registers are divided into two

groups. The Control and Status Registers (CSR) are

used to configure the Ethernet MAC engine and to ob-

tain status information. The Bus Control Registers

(BCR) are used to configure the bus interface unit and

the LEDs. Both sets of registers are accessed using in-

direct addressing.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data ports.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Port (BDP) is used to access a

BCR.

In order to access a particular CSR location, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then point to the selected CSR. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first be written with the appropriate BCR address. The

BDP will then point to the selected BCR. A read of the

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once the RAP has been written with a value, the RAP

value remains unchanged until another RAP write oc-

curs, or until an H_RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C972 controller allows for connection of a

serial EEPROM. The first 16 bytes of the EEPROM will

be automatically loaded into the Address PROM

(APROM) space after H_RESET. Additionally, the first

six bytes of the EEPROM will be loaded into CSR12 to

CSR14. The Address PROM space is a convenient

place to store the value of the 48-bit IEEE station ad-

dress. It can be overwritten by the host computer and

its content has no effect on the operation of the control-

ler. The software must copy the station address from

the Address PROM space to the initialization block in

Offset

Device ID

Vendor ID

00h

Status

Command

04h

Base-Class

Sub-Class

Programming IF

Revision ID

08h

Reserved

Header Type

Latency Timer

Reserved

0Ch

I/O Base Address

10h

Memory Mapped I/O Base Address

14h

Reserved

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Subsystem ID

Subsystem Vendor ID

2Ch

Expansion ROM Base Address

30h

Reserved

CAP-PTR

34h

Reserved

38h

MAX_LAT

MIN_GNT

Interrupt Pin

Interrupt Line

3Ch

PMC

NXT_ITM_PTR

CAP_ID

40h

DATA_REG

PMCSR_BSE

PMCSR

44H

Reserved

FCh

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