AM79C972BVCW datasheet(72/130 Pages) AMD

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Am79C972

External Address Detection Interface: External

PHY

When using the MII, the EADI interface changes to re-

flect the changes on that interface. Except for the nota-

tions below the interface conforms to the previous

functionality. The data arrives in nibbles and can be at

a rate of 25 MHz or 2.5 MHz.

The MII provides all necessary data and clock signals

needed for the EADI interface. Consequently, SRDCLK

and SRD are not used and are driven to 0. Data for the

EADI is the RXD(3:0) receive data provided to the MII.

Instead of deserializing the network data, the user will

receive the data as 4 bit nibbles. RX_CLK is provided

to allow clocking of the RXD(3:0) receive nibble stream

into the external address detection logic. The RXD(3:0)

data is synchronous to the rising edge of the RX_CLK.

The assertion of SFBD is a signal to the external ad-

dress detection logic that the SFD has been detected

and that the first valid data nibble is on the RXD(3:0)

data bus. The SFBD signal is delayed one RX_CLK

cycle from the above definition and actually signals the

start of valid data. In order to reduce the amount of

logic external to the Am79C972 controller for multiple

address decoding systems, the SFBD signal will go

HIGH at each new byte boundary within the packet,

subsequent to the SFD. This eliminates the need for ex-

ternally supplying byte framing logic.

The EAR pin function is the same and should be driven

LOW by the external address comparison logic to reject

a frame. See the External Address Detection Interface:

GPSI Port section for more details.

External Address Detection Interface: Receive

Frame Tagging

The Am79C972 controller supports receive frame tag-

ging in both GPSI or MII mode. The method remains

constant, but the chip interface pins will change be-

tween the MII and the GPSI modes. The receive frame

tagging implementation will be a two- and three-wire

chip interface, respectively, added to the existing EADI.

The Am79C972 controller supports up to 15 bits of re-

ceive frame tagging per frame in the receive frame sta-

tus (RFRTAG). The RFRTAG bits are in the receive

frame status field in RMD2 (bits 30-16) in 32-bit soft-

ware mode. The receive frame tagging is not supported

in the 16-bit software mode. The RFRTAG field are all

zeros when either the EADISEL (BCR2, bit3) or the

RXFRTAG (CSR7, bit 14) are set to 0. When EADISEL

(BCR2, bit 3) and RXFRTAG (CSR7, bit 14) are set to

1, then the RFRTAG reflects the tag word shifted in dur-

ing that receive frame.

In the MII mode, the two-wire interface will use the

MIIRXFRTGD and MIIRXFRTGE pins from the EADI

interface. These pins will provide the data input and

data input enable for the receive frame tagging, respec-

tively. These pins are normally not used during the MII

operation.

In the GPSI mode, the three-wire interface will use the

RXFRTGD, SRDCLK, and the RXFRTGE pins from the

EADI and MII. These pins will provide the data input,

data input clock, and the data input for the receive

frame tagging enable, respectively.

The receive frame tag register is a shift register that

shifts data in MSB first, so that less than the 15 bits al-

located may be utilized by the user. The upper bits not

utilized will return zeros. The receive frame tag register

is set to 0 in between reception of frames. After receiv-

ing SFBD indication on the EADI, the user can start

shifting data into the receive tag register until one net-

work clock period before the Am79C972 controller re-

ceives the end of the current receive frame.

In the MII mode, the user must see the RX_CLK to

drive the synchronous receive frame tag data interface.

After receiving the SFBD indication, sampled by the ris-

ing edge of the RX_CLK, the user will drive the data

input and the data input enable synchronous with the

rising edge of the RX_CLK. The user has until one net-

work clock period before the deassertion of the RX_DV

to input the data into the receive frame tag register. At

the deassertion of the RX_DV, the receive frame tag

terface. If the user is still driving the data input enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 37.

In the GPSI mode, the user must use the recovered re-

ceive data clock driven on the SRDCLK pin to drive the

synchronous receive frame tag data interface. After re-

ceiving the SFBD indication, sampled by the rising

edge of the recovered receive data clock, the user will

drive the data input and the data input enable synchro-

nous with the rising edge of the recovered receive data

clock. The user has until one network clock period be-

fore the deassertion of the data from the network to

input the data into the receive frame tag register. At the

completion of received network data, the receive frame

tag register will no longer accept data from the two-wire

interface. If the user is still driving the data input enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 38.

Table 8.

EADI Operations

PROM

EAR

Required

Timing

Received

Frames

No timing

requirements

All received frames

No timing

requirements

All received frames

Low for two bit

times plus 10 ns

Frame rejected if in

address match

mode

AM79C972BVCW Datasheet(PDF) 72 Page - Advanced Micro Devices

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