AM79C972BVCW datasheet(69/130 Pages) AMD

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Am79C972

to a 1, indicating the Am79C972 controller had an MII

management frame read error and that the data in

BCR34 is not valid. The data field to/from the external

PHY is read or written into the BCR34 register. The last

field is an IDLE field that is necessary to give ample

time for drivers to turn off before the next access. The

Am79C972 controller will drive the MDC to 0 and tri-

state the MDIO anytime the MII Management Port is

not active.

To help to speed up the reading and writing of the MII

management frames to the external PHY, the MDC can

be sped up to 10 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are

available for the user. The intended applications are

that the 10-MHz clock rate can be used for a single ex-

ternal PHY on an adapter card or motherboard. The 5-

MHz clock rate can be used for an exposed MII with

one external PHY attached. The 2.5-MHz clock rate is

intended to be used when multiple external PHYs are

connected to the MII Management Port or if compli-

ance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C972 controller’s MII has no

way of communicating important timely status informa-

tion back to Am79C972 controller. The Am79C972

controller has no way of knowing that an external PHY

has undergone a change in status without polling the

MII status register. To prevent problems from occurring

with i nadequate hos t or s o ftwar e pol ling, the

Am79C972 controller will Auto-Poll when APEP

(BCR32, bit 11) is set to 1 to insure that the most cur-

rent information is available. See Appendix C, MII

Management Registers, for the bit descriptions of the

MII Status Register. The contents of the latest read

from the external PHY will be stored in a shadow regis-

ter in the Auto-Poll block. The first read of the MII Status

be compared to the contents already stored in the

shadow register. If there has been a change in the con-

tents of the MII Status Register, a MAPINT (CSR7, bit

7) interrupt will be generated on INTA if the MAPINTE

(CSR7, bit 6) is set to 1. The Auto-Poll features can be

disabled if software driver polling is required.

The Auto-Poll’s frequency of generating MII manage-

ment frames can be adjusted by setting of the APDW

bits (BCR32, bits 10-8). The delay can be adjusted

from 0 MDC periods to 2048 MDC periods. Auto-Poll by

default will only read the MII Status register in the ex-

ternal PHY.

Network Port Manager

The Am79C972 controller is unique in that it does not

require software intervention to control and configure

an external PHY attached to the MII. This was done to

ensure backwards compatibility with existing software

drivers. To the current software drivers, the Am79C972

controller will look and act like the PCnet-PCI II and will

interoperate with existing PCnet drivers from revision

2.5 upward. The heart of this system is the Network

Port Manager.

If the external PHY is present and is active, the Net-

work Port Manager will request status from the external

PHY by generating MII management frames. These

frames will be sent roughly every 900 ms. These

frames are necessary so that the Network Port Man-

ager can monitor the current active link and can select

a different network port if the current link goes down.

Auto-Negotiation

Through the external PHY, the following capabilities are

possible: 100BASE-T4, 100BASE-TX Full-/Half-Du-

plex, and 10BASE-T Full-/Half-Duplex. The capabilities

are then sent to a link partner that will also send its ca-

pabilities. Both sides look to see what is possible and

then they will connect at the greatest possible speed

and capability as defined in the IEEE 802.3u standard

and according to Table 7.

By default, the link partner must be at least 10BASE-T

half-duplex capable. The Am79C972 controller can au-

tomatically negotiate with the network and yield the

highest performance possible without software sup-

port. See the section on Network Port Manager for

more details.

Auto-Negotiation goes further by providing a message-

based communication scheme called, Next Pages, be-

fore connecting to the Link Partner. This feature is not

supported in Am79C972 unless the DANAS (BCR32,

bit 10) is selected and the software driver is capable of

controlling the external PHY. A complete bit description

of the MII and Auto-Negotiation registers can be found

in Appendix C.

Automatic Network Port Selection

If ASEL (BCR2, bit 0) is set to 1 and DANAS (BCR 32,

bit 7) is set to 0, then the Network Port Manager will

start to configure the external PHY if it detects the ex-

ternal PHY on the MII Interface.

Table 7.

Auto-Negotiation Capabilities

Network Speed

Physical Network Type

200 Mbps

100BASE-X, Full Duplex

100 Mbps

100BASE-T4, Half Duplex

100 Mbps

100BASE-X, Half Duplex

20 Mbps

10BASE-T, Full Duplex

10 Mbps

10BASE-T, Half Duplex

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