AM79C972BVCW datasheet(1/130 Pages) AMD

Part #	AM79C972BVCW

Description	PCnet??FAST Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

PDF	130 Pages

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Manufacturer	AMD [Advanced Micro Devices]

Direct Link	http://www.amd.com

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1 / 130 page

Publication# 21485

Rev: D Amendment/0

Issue Date: December 1999

Refer to AMD’s Website (www.amd.com) for the latest information.

Am79C972

PCnet™-FAST+

Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

DISTINCTIVE CHARACTERISTICS

n Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

— 32-bit glueless PCI host interface

— Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

— PCI specification revision 2.1 compliant

— Supports PCI Subsystem/Subvendor ID/

Vendor ID programming through the

EEPROM interface

— Supports both PCI 3.3-V and 5.0-V signaling

environments

— Plug and Play compatible

— Supports an unlimited PCI burst length

— Big endian and little endian byte alignments

supported

— Implements optional PCI power management

event (PME) pin

n Media Independent Interface (MII) for

connecting external 10/100 megabit per second

(Mbps) transceivers

— IEEE 802.3-compliant MII

— Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3-

compliant MII PHYs at full- or half-duplex

n Supports General Purpose Serial Interface

(GPSI) with receive frame tagging support for

internetworking applications

n Full-duplex operation supported in MII and GPSI

ports with independent Transmit (TX) and

Receive (RX) channels

n Supports PC97, PC98, and Net PC requirements

— Implements full OnNow features including

pattern matching and link status wake-up

— Implements Magic Packet mode

— Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

— Supports PCI Bus Power Management

Interface Specification Version 1.0

— Supports Advanced Configuration and

Power Interface (ACPI) Specification

Version 1.0

— Supports Network Device Class Power

Management Specification Version 1.0

n Large independent internal TX and RX FIFOs

— Programmable FIFO watermarks for both

transmit and receive operations

— Receive frame queuing for high latency PCI

bus host operation

— Programmable allocation of buffer space

between transmit and receive queues

n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 and Blue Book Ethernet

standards

n EEPROM interface supports jumperless design

and provides through-chip programming

— Supports full programmability of half-/full-

duplex operation for external 10/100 Mbps

PHYs through EEPROM mapping

— Programmable PHY reset output pin capable

of resetting external PHY without needing

buffering

n Integrated oscillator circuit eliminates need for

external crystal

n Extensive programmable LED status support

n Support for operation in industrial temperature

range (-40°C to +85°C)

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