AM79C972BVCW datasheet(64/130 Pages) AMD

64 / 130 page

Am79C972

frames which have a length field of 46 bytes or greater

will be passed to the host unmodified.

Figure 34 shows the byte/bit ordering of the received

length field for an IEEE 802.3-compatible frame format.

Figure 34.

IEEE 802.3 Frame And Length Field Transmission Order

Since any valid Ethernet Type field value will always be

greater than a normal IEEE 802.3 Length field (

≥46),

the Am79C972 controller will not attempt to strip valid

Ethernet frames. Note that for some network protocols,

the value passed in the Ethernet Type and/or IEEE

802.3 Length field is not compliant with either standard

and may cause problems if pad stripping is enabled.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the Am79C972 controller.

Note that if the Automatic Pad Stripping feature is en-

abled, the FCS for padded frames will be verified

against the value computed for the incoming bit stream

including pad characters, but the FCS value for a pad-

ded frame will not be passed to the host. If an FCS

error is detected in any frame, the error will be reported

in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories, i.e., those conditions which are the

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal events which may occur and which are handled

autonomously by the Am79C972 controller are basi-

cally collisions within the slot time and automatic runt

packet rejection. The Am79C972 controller will ensure

that collisions that occur within 512 bit times from the

start of reception (excluding preamble) will be automat-

ically deleted from the receive FIFO with no host inter-

vention. The receive FIFO will delete any frame that is

composed of fewer than 64 bytes provided that the

Runt Packet Accept (RPA bit in CSR124) feature has

not been enabled and the network interface is operat-

ing in half-duplex mode, or the full-duplex Runt Packet

Accept Disable bit (FDRPAD, BCR9, bit 2) is set. This

criterion will be met regardless of whether the receive

frame was the first (or only) frame in the FIFO or if the

receive frame was queued behind a previously re-

ceived message.

Abnormal network conditions include:

n FCS errors

n Late collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

section, Buffer Management Unit.

Loopback Operation

Loopback is a mode of operation intended for system

diagnostics. In this mode, the transmitter and receiver

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length

LLC

Data

Pad

FCS

Bytes

46 — 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing Time

Bit

Most

Significant

Byte

Least

Significant

Byte

1 — 1500

Bytes

45 — 0

Bytes

21485C-37

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