AM79C972BVCW datasheet(84/130 Pages) AMD

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Am79C972

Table 11.

LED Default Configuration

For each LED register, each of the status signals is

AND’d with its enable signal, and these signals are all

OR’d together to form a combined status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shift register is normally at logic 0. The OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asserted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 47.

Power Savings Mode

Power Management Support

PCnet-FAST+ supports power management as defined

in the PCI Bus Power Management Interface Specifica-

tion V1.0 and Network Device Class Power Manage-

me nt R e f e r e n c e Specif icatio n V1. 0 .T he s e

specifications define the network device power states,

PCI power management interface including the Capa-

bilities Data Structure and power management regis-

ters block definitions, power management events, and

On Now netwo r k Wa ke -up events. In addition,

PCnet-FAST+ supports legacy power management

schemes, such as Remote Wake-Up (RWU) mode.

When the system is in RWU mode, PCI bus power is

on, the PCI clock may be slowed down or stopped, and

the wake-up output pin may drive the CPU's System

Management Interrupt (SMI) line.

Figure 47.

LED Control Logic

The general scheme for the PCnet-FAST+ power man-

agement is that when a PCI Wake-up event is detected,

a signal is generated to cause hardware external to the

PCnet-FAST+ device to put the computer into the work-

ing (S0) mode.

The PCnet-FAST+ device supports three types of

wake-up events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change

Figure 48 shows the relationship between these Wake-

up events and the various outputs used to signal to the

external hardware.

Note: The OnNOW Pattern Match and Link State

Change only work on the MII interface.

OnNow Wake-Up Sequence

The system software enables the PME pin by setting

the PME_EN bit in the PMCSR register (PCI configura-

tion registers, offset 44h, bit 8) to 1. When a Wake-up

event is detected, the PCnet-FAST+ device sets the

PME_STATUS bit in the PMCSR register (PCI configu-

ration registers, offset 44h, bit 15). Setting this bit

causes the PME signal to be asserted. Assertion of the

PME signal causes external hardware to wake up the

CPU. The system software then reads the PMCSR reg-

ister of every PCI device in the system to determine

which device asserted the PME signal.

LED

Output

Indication

Driver Mode

Pulse Stretch

LED0

Link Status

Open Drain -

Active Low

Enabled

LED1

Receive

Status

Open Drain -

Active Low

Enabled

LED2

Open Drain -

Active Low

Enabled

LED3

Transmit

Status

Open Drain -

Active Low

Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

_SPEED_SEL

100E

MPS

MPSE

21485C-50

AM79C972BVCW Datasheet(PDF) 84 Page - Advanced Micro Devices

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