AM79C975 datasheet(45/304 Pages) AMD

45 / 304 page

Am79C973/Am79C975

P R E L I M INARY

If the host is not yet ready when the Am79C973/

Am79C975 controller asserts TRDY, the device will

wait for the host to assert IRDY. When the host asserts

IRDY and FRAME is still asserted, the Am79C973/

Am79C975 controller will finish the first data phase by

deasserting TRDY one clock later. At the same time, it

will assert STOP to signal a disconnect to the host.

STOP will stay asser ted until the host removes

FRAME. See Figure 8.

Figure 8. Disconnect Of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C973/Am79C975 controller is not the

current bus master, it samples the AD[31:0], C/BE[3:0],

and the PAR lines during the address phase of any PCI

command for a parity error. When it detects an address

parity error, the controller sets PERR (PCI Status reg-

ister, bit 15) to 1. When reporting of that error is en-

abled by setting SERREN (PCI Command register, bit

8) and PERREN (PCI Command register, bit 6) to 1, the

Am79C973/Am79C975 controller also drives the

SERR signal low for one clock cycle and sets SERR

(PCI Status register, bit 14) to 1. The assertion of

SERR follows the address phase by two clock cycles.

The Am79C973/Am79C975 controller will not assert

DEVSEL for a PCI transaction that has an address par-

ity error when PERREN and SERREN are set to 1. See

Figure 9.

Figure 9. Address Parity Error Response

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that selects

the Am79C973/Am79C975 controller as target, the de-

vice samples the AD[31:0] and C/BE[3:0] lines for par-

ity on the clock edge, and data is transferred as

indicated by the assertion of IRDY and TRDY. PAR is

sampled in the following clock cycle. If a parity error is

detected and reporting of that error is enabled by set-

ting PERREN (PCI Command register, bit 6) to 1,

PERR is asserted one clock later. The parity error will

always set PERR (PCI Status register, bit 15) to 1 even

when PERREN is cleared to 0. The Am79C973/

Am79C975 controller will finish a transaction that has a

data parity error in the normal way by asserting TRDY.

The corrupted data will be written to the addressed lo-

cation.

Figure 10 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY

and TRDY are both asserted). PERR is driven high at

the beginning of the data phase and then drops low due

to the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C973/Am79C975 controller drives PERR high for

one clock cycle, since PERR is a sustained tri-state sig-

nal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

23456

PAR

DATA

1st DATA

21510D-13

FRAME

CLK

SERR

C/BE

DEVSEL

2345

PAR

ADDR

1st DATA

CMD

PAR

21510D-14

AM79C975 Datasheet(PDF) 45 Page - Advanced Micro Devices

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