AM79C975 datasheet(69/304 Pages) AMD

69 / 304 page

Am79C973/Am79C975

P R E L I M INARY

If a poll operation has revealed that the current and the

next RDTE belong to the Am79C973/Am79C975 con-

troller, then additional poll accesses are not necessary.

Future poll operations will not include RDTE accesses

as long as the Am79C973/Am79C975 controller re-

tains ownership of the current and the next RDTE.

When receive activity is present on the channel, the

Am79C973/Am79C975 controller waits for the com-

plete address of the message to arrive. It then decides

whether to accept or reject the frame based on all ac-

tive addressing schemes. If the frame is accepted, the

Am79C973/Am79C975 controller checks the current

receive buffer status register CRST (CSR41) to deter-

mine the ownership of the current buffer.

If ownership is lacking, the Am79C973/Am79C975

controller will immediately perform a final poll of the

current RDTE. If ownership is still denied, the

Am79C973/Am79C975 controller has no buffer in

which to store the incoming message. The MISS bit will

be set in CSR0 and the Missed Frame Counter

(CSR112) will be incremented. Another poll of the cur-

rent RDTE will not occur until the frame has finished.

If the Am79C973/Am79C975 controller sees that the

last poll (either a normal poll, or the final effort de-

scribed in the above paragraph) of the current RDTE

shows valid ownership, it proceeds to a poll of the next

RDTE. Following this poll, and regardless of the out-

come of this poll, transfers of receive data from the

FIFO may begin.

Regardless of ownership of the second receive de-

scriptor, the Am79C973/Am79C975 controller will con-

tinue to perform receive data DMA transfers to the first

buffer. If the frame length exceeds the length of the first

buffer, and the Am79C973/Am79C975 controller does

not own the second buffer, ownership of the current de-

scriptor will be passed back to the system by writing a

0 to the OWN bit of RMD1. Status will be written indi-

cating buffer (BUFF = 1) and possibly overflow (OFLO

= 1) errors.

If the frame length exceeds the length of the first (cur-

rent) buffer, and the Am79C973/Am79C975 controller

does own the second (next) buffer, ownership will be

passed back to the system by writing a 0 to the OWN

bit of RMD1 when the first buffer is full. The OWN bit is

the only bit modified in the descriptor. Receive data

transfers to the second buffer may occur before the

Am79C973/Am79C975 controller proceeds to look

ahead to the ownership of the third buffer. Such action

will depend upon the state of the FIFO when the OWN

bit has been updated in the first descriptor. In any case,

lookahead will be performed to the third buffer and the

information gathered will be stored in the chip, regard-

less of the state of the ownership bit.

This activity continues until the Am79C973/Am79C975

controller recognizes the completion of the frame (the

last byte of this receive message has been removed

from the FIFO). The Am79C973/Am79C975 controller

will subsequently update the current RDTE status with

the end of frame (ENP) indication set, write the mes-

sage byte count (MCNT) for the entire frame into

RMD2, and overwrite the “current” entries in the CSRs

with the “next” entries.

Receive Frame Queuing

The Am79C973/Am79C975 controller supports the

lack of RDTEs when SRAM (SRAM SIZE in BCR 25,

bits 7-0) is enabled through the Receive Frame Queu-

ing mechanism. When the SRAM SIZE = 0, then the

Am79C973/Am79C975 controller reverts back to the

PCnet PCI II mode of operation. This operation is auto-

matic and does not require any programming by the

host. When SRAM is enabled, the Receive Frame

Queuing mechanism allows a slow protocol to manage

more frames without the high frame loss rate normally

attributed to FIFO based network controllers.

The Am79C973/Am79C975 controller will store the in-

coming frames in the extended FIFOs until polling

takes place; if enabled, it discovers it owns an RDTE.

The stored frames are not altered in any way until writ-

ten out into system buffers. When the receive FIFO

overflows, further incoming receive frames will be

missed during that time. As soon as the network re-

ceive FIFO is empty, incoming frames are processed

as normal. Status on a per frame basis is not kept dur-

ing the overflow process. Statistic counters are main-

tained and accurate during that time.

During the time that the Receive Frame Queuing mech-

anism is in operation, the Am79C973/Am79C975 con-

troller relies on the Receive Poll Time Counter (CSR

48) to control the worst case access to the RDTE. The

Receive Poll Time Counter is programmed through the

Receive Polling Interval (CSR49) register. The Re-

ceived Polling Interval defaults to approximately 2 ms.

The Am79C973/Am79C975 controller will also try to

access the RDTE during normal descriptor accesses

whether they are transmit or receive accesses. The

host can force the Am79C973/Am79C975 controller to

immediately access the RDTE by setting the RDMD

(CSR 7, bit 13) to 1. Its operation is similar to the trans-

mit one. The polling process can be disabled by setting

the RXDPOLL (CSR7, bit 12) bit. This will stop the au-

tomatic polling process and the host must set the

RDMD bit to initiate the receive process into host mem-

ory. Receive frames are still stored even when the re-

ceive polling process is disabled.

Software Interrupt Timer

The Am79C973/Am79C975 controller is equipped with

a software programmable free-running interrupt timer.

The timer is constantly running and will generate an in-

terrupt STINT (CSR 7, bit 11) when STINITE (CSR 7,

bit 10) is set to 1. After generating the interrupt, the

AM79C975 Datasheet(PDF) 69 Page - Advanced Micro Devices

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