AM79C975 datasheet(67/304 Pages) AMD

67 / 304 page

Am79C973/Am79C975

P R E L I M INARY

Figure 32. 32-Bit Software Model

If RXON is cleared to 0, the Am79C973/Am79C975

controller will never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs should be available. In this case, the

poll operation will only consist of the check of the status

of the current TDTE.

A typical transmit poll is the product of the following

conditions:

1. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 (CSR4, bit 12) and

TXON = 1 (CSR0, bit 4) and

the poll time has elapsed, or

2. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been received, or

3. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delayed until the microcode returns to the

poll counting code.

The user may change the poll time value from the de-

fault of 65,536 clock periods by modifying the value in

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the Am79C973/Am79C975 controller finds that

the OWN bit of that TDTE is not set, the Am79C973/

Am79C975 controller resumes the poll time count and

re-examines the same TDTE at the next expiration of

the poll time count.

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C973/Am79C975

controller will immediately request the bus in order to

clear the OWN bit of this descriptor. (This condition

would normally be found following a late collision

(LCOL) or retry (RTRY) error that occurred in the mid-

dle of a transmit frame chain of buffers.) After resetting

Initialization

Block

CSR1

CSR2

RMD

Rcv Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

RMD

TMD0

TMD1 TMD2 TMD3

Xmt Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16]

IADR[15:0]

TLE RES RLE RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

21510D-37

AM79C975 Datasheet(PDF) 67 Page - Advanced Micro Devices

AM79C975 Datasheet(HTML) 67 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL