AM79C975 datasheet(80/304 Pages) AMD

80 / 304 page

Am79C973/Am79C975

P R E L I M INARY

PHY/MAC Interface

The internal MII-compatible interface provides the data

path connection between the 10/100 PHY and 10/100

Media Access Control (MAC). The interface is compat-

ible with Clause 22 of the IEEE 802.3 standard specifi-

cation.

Transmit Process

The transmit process generates code-groups based on

TXD[3:0], TX_EN, TX_ER signals on the internal MII.

These code-groups are transmitted by the PDX block.

This process is also responsible for frame encapsula-

tion into a Physical Layer Stream, generating the colli-

sion signal based on whether a carrier is received

simultaneously with transmission and generating the

Carrier Sense (CRS) and Collision (COL) signals at the

internal MII. The transmit process is implemented in

compliance with the transmit state diagram as defined

in Clause 24 of the IEEE 802.3u specification. Figure

38 shows the transmit process.

Receive Process

The receive process passes to the internal MII a se-

quence of data nibbles derived from the incoming

code-groups. Each code-group is comprised of five

code-bits. This process detects channel activity and

then aligns the incoming code bits in code-group

boundaries for subsequent data decoding. The receive

process is responsible for code-group alignment and

also generates the Carrier Sense (CRS) signal at the

internal MII. The receive process is implemented in

compliance with the receive state diagram as defined in

Clause 24 of the IEEE 802.3u specification. The False

Carrier Indication as specified in the standard is also

generated by this block, and communicated to the Rec-

onciliation layer. Figure 38 shows the receive process.

Internal PHY Loopback Path

As shown in Figure 35, the 10/100 PHY provides an

internal loopback path for system testing purposes.

The loopback option utilizes the serial loopback path

from the PDX serial output to the PDX serial input and

can be programmed via the LBK[1:0] bits in the PHY

Control/Status Register (ANR17).

For the corresponding LBK setting, refer to the descrip-

tion for the PHY Control/Status Register.

AM79C975 Datasheet(PDF) 80 Page - Advanced Micro Devices

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