AM79C975 datasheet(85/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Figure 36. MLT-3 Waveform

Serializer/Deserializer and Clock Recovery

The Physical Data Transceiver (PDX) is a CMOS all

digital core that is used in the 10/100 PHY. It employs

new circuit techniques to achieve clock and data recov-

ery.

Traditionally, Phase-Locked-Loops (PLLs) are used for

the purpose of clock recovery in data communication

areas. There are both analog and digital versions of the

PLL components such as phase detector, filter, and

charge pump. A traditional PLL always contains a volt-

age-controlled oscillator (VCO) to regenerate a clock

which is synchronized in frequency to and aligned in

phase with the received data.

The PDX employs techniques that are significantly dif-

ferent from traditional PLLs. Not only are the control

functions completely digital, the VCO function is also

replaced by a proprietary delay time ruler technique.

The result is a highly integratible core which can be

manufactured in a standard digital CMOS process.

To transmit, the PDX accepts 4B/5B encoded data

symbols from the scrambler. The 5-bit symbol is

clocked into the PDX by the rising edge of the 25-MHz

clock, serialized and converted to NRZI format. The

NRZI data is delivered to the PECL transceiver or MLT3

transceiver. The output of either of the two transceivers

goes to the TX± pair.

The PDX uses a 25-MHz clock as the frequency and

phase reference to generate the serial link data rate.

The external clock source must be continuous. All of

the internal logic of the PDX runs on an internal clock

that is derived from the external reference source. The

PDX’s clock multiplier is referenced to the rising edges

of the 25-MHz clock only.

In order to generate the serial output wave forms con-

forming to the specifications, the external reference

clock must meet 100BASE-X frequency and stability

requirements. Under normal conditions, the frequency

of the 25-MHz clock multiplied by 5 must be within the

100BASE-X specified 100 ppm of the received data for

the PDX to operate optimally.

Note: The 100 ppm is the tolerance of the crystal-con-

trolled source.

The TX± serial output typically contains less than

0.4 ns peak-to-peak jitter at 125 Mbaud.

Receiving from the physical medium through the PMD

device, the PDX accepts encoded PECL NRZI signal

levels at the RX± inputs. The receiver circuit recovers

data from the input stream by regenerating clocking in-

formation embedded in the serial stream. The recov-

ered clock is called RSCLK (an internal signal). The

PDX then clocks the unframed symbol (5 bits) to the

descrambler interface on the falling edge of RSCLK.

The PDX receiver uses advanced circuit techniques to

extract encoded clock information from the serial input

stream and recovers the data. Its operating frequency

is established by the reference clock at 25 MHz. The

PDX is capable of recovering data correctly within

±1000 ppm of the 25-MHz clock signal (which exceeds

the frequency range defined by the 100BASE-X speci-

fication). The 100BASE-X 4B/5B encoding scheme en-

sures run-length limitation and adequate transition

density of the encoded data stream, while TP-PMD

achieves this on a statistical basis through data scram-

bling. The PDX clock recovery circuit is designed to tol-

erate a worst-case run-length of 60-bits in order to

function correctly with both fiber-optic and twisted-pair

PMDs.

The PDX receiver has input jitter tolerance characteris-

tics that meet or exceed the recommendations of Phys-

ical Layer Medium Dependent (PMD) 100BASE-X

document. Typically, at 125 Mbaud (8 ns/bit), the peak-

to-peak Duty-Cycle Distortion (DCD) tolerance is

1.4 ns, the peak-to-peak Data Dependent Jitter (DDJ)

tolerance is 2.2 ns, and the peak-to-peak Random Jit-

ter (RJ) tolerance is 2.27 ns. The total combined peak-

to-peak jitter tolerance is typically 5 ns with a bit error

rate (BER) better than 2.5 x 10-10.

Medium Dependent Interface

The Am79C973/Am79C975 device connects directly to

low cost magnetics modules for interface to twisted pair

media (UTP and/or STP). The TX± and RX± pins pro-

vide the interface for both 10BASE-T and 100BASE-TX

allowing the use of a 1:1.41 (transmit) and 1:1 (receive)

transformer with single primary and secondary wind-

ings. No filtering is required in the magnetics module.

Refer to Figure 37 for recommended termination.

21510D-41

MLT-3

1010101

8 ns

AM79C975 Datasheet(PDF) 85 Page - Advanced Micro Devices

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