EP2C8A datasheet(119/168 Pages) ALTERA

119 / 168 page

Altera Corporation

5–29

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

EP2C70 Clock Timing Parameters

Tables 5–33 and 5–34 show the clock timing parameters for EP2C70

devices.

Clock Network Skew Adders

Table 5–35 shows the clock network specifications.

Table 5–33. EP2C70 Column Pins Global Clock Timing Parameters

Parameter

Fast Corner

–6 Speed

Grade

–7 Speed

Grade

–8 Speed

Grade

Unit

Industrial

Commercial

tCIN

1.575

1.651

2.914

3.105

3.174

tCOUT

1.589

1.666

2.948

3.137

3.203

tPL LCIN

–0.149

–0.158

0.27

0.268

0.089

tPL LCOUT

–0.135

–0.143

0.304

0.3

0.118

Table 5–34. EP2C70 Row Pins Global Clock Timing Parameters

Parameter

Fast Corner

–6 Speed

Grade

–7 Speed

Grade

–8 Speed

Grade

Unit

Industrial

Commercial

tCIN

1.463

1.533

2.753

2.927

3.010

tCOUT

1.465

1.535

2.769

2.940

3.018

tPL LCIN

–0.261

–0.276

0.109

0.09

–0.075

tPL LCOUT

–0.259

–0.274

0.125

0.103

–0.067

Table 5–35. Clock Network Specifications

Name

Description

Max

Unit

Clock skew adder

EP2C5/A, EP2C8/A (1)

Inter-clock network, same bank

±88

Inter-clock network, same side and

entire chip

±88

Clock skew adder

EP2C15A, EP2C20/A,

EP2C35, EP2C50,

EP2C70 (1)

Inter-clock network, same bank

±118

Inter-clock network, same side and

entire chip

±138

Note to Table 5–35:

(1)

This is in addition to intra-clock network skew, which is modeled in the

Quartus II software.

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