EP2C8A datasheet(121/168 Pages) ALTERA

121 / 168 page

Altera Corporation

5–31

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Default Capacitive Loading of Different I/O Standards

Refer to Table 5–38 for default capacitive loading of different I/O

standards.

Input Delay

from Pin to

Input

Pad ->

I/O input

2669

4482

4834

4859

2802

—

4671

—

Delay from

Output

Output Pin

I/O

output

> Pad

308

572

648

682

324

—

626

—

Notes to Table 5–37 :

(1)

The incremental values for the settings are generally linear. For exact values of each setting, use the latest version

of the Quartus II software.

(2)

The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II

software.

(3)

The value in the first row represents the fast corner timing parameter for industrial and automotive devices. The

second row represents the fast corner timing parameter for commercial devices.

(4)

The value in the first row is for automotive devices. The second row is for commercial devices.

Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 2 of 2)

Parameter

Paths

Affected

Number

Settings

Fast Corner (3)

–6 Speed

Grade

–7 Speed

Grade (4)

–8 Speed Grade

Unit

Min

Offset

Max

Offset

Min

Offset

Max

Offset

Min

Offset

Max

Offset

Min

Offset

Max

Offset

Table 5–38. Default Loading of Different I/O Standards for Cyclone II Device

(Part 1 of 2)

I/O Standard

Capacitive Load

Unit

LVTTL

LVCMOS

2.5V

1.8V

1.5V

PCI

PCI-X

SSTL_2_CLASS_I

SSTL_2_CLASS_II

SSTL_18_CLASS_I

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