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AS3658 Datasheet(PDF) 97 Page - ams AG |
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AS3658 Datasheet(HTML) 97 Page - ams AG |
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97 / 158 page ![]() Table 99. i2s master control1 Register Addr:131 I2s master control1 This register controls the external clock divider for i2s master mode Bit Bit Name Default Access Description www.austriamicrosystems.com Revision 1v13 96 - 157 AS3658 Data Sheet Confidential - Detail ed Descri ption- Audio Functi ons 11,025 12288 555,28 555 11,03 0,05 8,000 12288 766,00 766 8,00 0,00 48,000 12000 123,00 123 48,00 0,00 44,100 12000 134,05 134 44,12 0,04 32,000 12000 185,50 186 31,91 -0,27 29,400 12000 202,08 202 29,41 0,04 24,000 12000 248,00 248 24,00 0,00 22,050 12000 270,11 270 22,06 0,04 12,000 12000 498,00 498 12,00 0,00 11,025 12000 542,22 542 11,03 0,04 8,000 12000 748,00 748 8,00 0,00 7:0 i2s_clk_divider<7:0> 00h R/W Bit 7:0 of divider for MCLK2 input pin Table 100. i2s master control2 Register Addr:132 I2s master control2 This register controls the external clock divider and modes for i2s master mode Bit Bit Name Default Access Description 2:0 i2s_clk_divider<10:8> 000b R/W Bit 10:8 of divider for MCLK2 input pin 3 i2s_master_on 0b R/W 0 i2s master mode disabled 1 i2s master mode enabled 4 i2s_lrclk_sclk_out_en 0b R/W 0 LRCLK1 and SCLK1 are used as input (slave mode) 1 LRCLK1 and SCLK1 are used as output (master mode). Clock input for PLL is MCLK2 5 i2s_mclk_out_en 0b R/W 0 MCLK1 used as input (slave mode) 1 MCLK1 used as output for master clock of an external I2S. Clock input for PLL is MCLK2 (MCLK1=256*LRCLK, if bit mclk256=1; MCLK=128*LRCLK, if bit mclk256=0) 6 sdo_on_ mclk1 0b R/W 0 Normal operation of MCLK1 (input or output according to bit is2_mclk_out_en bit) 1 MCLK1 used as SDO output (e.g. for audio ADC). May be used as data output (SDO) for I2S_2 port Table 98. PLL,i2s_clk_divider settings Sample rate MCLK2 input Divider i2s_clk_divider <10:0> Actual sample rate Error kHz kHz kHz % |
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