TS68302VR16 datasheet(17/47 Pages) ATMEL

17 / 47 page

TS68302

2117A–HIREL–11/02

Figure 9. Bus Arbitration Timing Diagram

Note:

Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, and IPL2-IPL0 guarantees their recog-

nition at the next falling edge of the clock.

Notes:

1. DREQ is sampled on the falling edge of CLK in cycle steal and burst modes.

2. If #80 is satisfied for DREQ, #81 may be ignored.

3. BR will not be asserted while AS, HALT, or BERR is asserted.

4. Specifications are for DISABLE CPU mode only.

CLKO

57 57A

58 58A

37A

STROBES

AND R/W

BGACK

Table 9. AC Electrical Specifications - DMA (see Figure 10) f = 16.67 MHz

Num.

Symbol

Parameter

Min

Max

Unit

REQASI

DREQ asynchronous setup time

(1)

tREQL

DREQ width low

(2)

2clk

REQLBRL

DREQ low to BR low

(3)(4)

2clk

CHBRL

Clock high to BR low

(3)(4)

tCHBRZ

Clock high to BR high impedance

(3)(4)

BKLBRZ

BGACK low to BR high impedance

(3)(4)

CHBKL

Clock high to BGACK low

tABHBKL

AS and BGACK high (the latest one) to BGACK low (when

BG is asserted)

1.5

2.5

+ 30

clk

BGLBKL

AS low to BGACK low (no other bus master)

(3)(4)

2.5

+ 30

clk

BRHBGH

BR high impedance to BG high

(3)(4)

0ns

CLBKLAL

Clock on which BGACK low to clock on which AS low

clk

tCHBKH

Clock high to BGACK high

CLBKZ

Clock low to BGACK high impedance

CHACKL

Clock high to DACK low

tCLACKH

Clock high to DACK high

CHDNL

Clock high to DONE low (output)

CLDNZ

Clock low to DONE high impedance

DNLTCH

DONE input low to clock high (asynchronous setup)

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