32

TS68302

2117A–HIREL–11/02

Notes:

1. The ratio CLK/TCLK1 and CLK/RCLK1 must be greater than 2.5/1 for external clock. For internal clock the ratio must be

greater than 3/1 (the input clock to the baud rate generator may be either CLK or TIM1), in both cases the maximum fre-

quency is limited to 16.67 MHz. In asynchronous mode (UART), the bit rate is 1/16 of the clock rate.

2. Schmitt triggers used on input buffers.

3. Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode.

4. See Figure 26.

Figure 25. PCM Timing Diagram

Table 22. AC Electrical Specifications - NMSI Timing

(4)

The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be internal or external. When the

clock is internal, it is generated by the internal baud rate generator and it is output on L1R x D or L1T x D. All the timing is

related to the external clock pin. The timing is specified for NMSI1. It is also valid for NMS12 and NMS13.

Num.

Parameter

Internal Clock

External Clock

Unit

Min

Max

Min

Max

315

RCLK1 and TCLK1 frequency

(1)

5.12

6.668

MHz

316

RCLK1 and TCLK1 low/high

70

55

ns

317

RCLK1 and TCLK1 rise/fall time

(2)

————

ns

318

T x D1 active delay TCLK1 falling edge

0

40

0

70

ns

319

RTS1 active/inactive delay from TCLK1 falling edge

0

40

0

100

ns

320

CTS1 setup time to TCLK1 rising edge

50

10

ns

321

R x D1 setup time to RCLK1 rising edge

50

10

ns

322

R x D1 hold time from RCLK1 rising edge

(3)

10

50

ns

323

CD1 setup time to RCLK1 rising edge

50

10

ns

302

300

310

301

305

304

307

306

309

308

302

303

311

307

L1CLK

(INPUT)

L1SY0

L1SY1

(INPUT)

L1SY0

L1SY1

(INPUT)

L1TXD

(OUTPUT)

L1TXD

(OUTPUT)

L1RXD

(INTPUT)

SYNC ENVELOPES DATAS

1

234

56

7

8

9

1

234

56

7

8

9

1

234

56

7

8

1

2

3

4

5

6

7

8

91011