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TS68302VR16 Datasheet(PDF) 3 Page - ATMEL Corporation |
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TS68302VR16 Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 47 page  3 TS68302 2117A–HIREL–11/02 Figure 1. TS68302 Block Diagram TS68000/TS68008 CORE TS68000 BUS INTERRUPT CONTROLLER BUS ARBITER TIMERS (3) PARALLEL I/O 1152 BYTES DUAL-PORT STATIC RAM CHIP-SELECT AND WAIT- STATE LOGIC SYSTEM CONTROL CLOCK GENERATOR ON-CHIP PERIPHERALS BUS INTERFACE UNIT SERIAL CHANNELS PHYSICAL INTERFACE I/O PORTS AND PIN ASSIGNEMENTS COMMUNICATIONS PROCESSOR MAIN CONTROLLER (RISC) SDMA (6 CHANNELS) SMC (2) SCC1 SCC2 SCC3 SCP PERIPHERAL BUS SYSTEM INTEGRATION BLOCK IDMA (1 CHANNEL) DRAM REFRESH CONTROLLER TS68000/TS68008 CORE |
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