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TS68302VR16 Datasheet(PDF) 18 Page - ATMEL Corporation |
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TS68302VR16 Datasheet(HTML) 18 Page - ATMEL Corporation |
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18 / 47 page  18 TS68302 2117A–HIREL–11/02 Figure 10. DMA Timing Diagram Note: 1. If AS is negated before DS, the data bus could be three-stated (spec 126) before DS is negated. 2. See Figure 11 and Figure 12. Table 10. AC Electrical Specifications - External Master Internal Asynchronous Read/write Cycles (2) f = 16.67 MHz Num. Symbol Parameter Min Max Unit 100 tRWVDSL R/W valid to DS low 0 ns 101 t DSLDIV DS low to data in valid 30 ns 102 t DKLDH DTACK low to data in hold time 0 ns 103 tASVDSL AS valid to DS low 0 ns 104 t DKLDSH DTACK low to DS high 0 ns 105 t DSHDKH DS high to DTACK high 45 ns 106 tDSIASI DS inactive to AS inactive 0 ns 107 t DSHRWH DS high to R/W high 0 ns 108 t DSHDZ DS high to data high impedance 45 ns 108A tDSHDH DS high to data out hold time 0 ns 109 t DSHDOH DS high to data in hold time (1) 0ns 109A t DOVDKL Data out valid to DTACK low 15 ns |
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