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TS68302VR16 Datasheet(PDF) 29 Page - ATMEL Corporation |
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TS68302VR16 Datasheet(HTML) 29 Page - ATMEL Corporation |
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29 / 47 page ![]() 29 TS68302 2117A–HIREL–11/02 Notes: 1. The ratio CLK/L1CLK must be greater than 2.5/1. 2. High impedance is measured at the 30% and 70% of VDD points, with the line at VDD/2 through 10K in parallel with 130 pF. 3. See Figure 23. Figure 23. IDL Timing Diagram 274 L1GR hold time (from L1SY1 falling edge) 50 ns 275 SDS1-SDS2 active delay from L1CLK rising edge 10 75 ns 276 SDS1-SDS2 inactive delay from L1CLK falling edge 10 75 ns Table 19. AC Electrical Specifications - Idle Timing(3) f = 16.67 MHz All timing measurements, unless otherwise specified, are referenced to the L1CLK at 50% point of VDD (Continued) Num. Parameter Min Max Unit (OUTPUT) L1CLK (INPUT) L1RXD L1SY1 (INPUT) SDS1 SDS2 (OUTPUT) L1TXD L1RQ (OUTPUT) L1GR (INPUT) 265 261 263 272 268 (INPUT) 273 269 267 264 270 260 B10 276 D1 B10 B11 AB27 B26 B25 B24 B23 B22 B21 B20 D2 M B17 B15 B14 B12 B13 B16 D1 B11 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M B17 B15 B14 B12 B13 B16 275 262 266 271 274 1 2 3 456789 10 11 12 13 14 15 16 17 18 19 20 |
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