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TS68302VR16 Datasheet(PDF) 28 Page - ATMEL Corporation

Part # TS68302VR16
Description  Integrated Multiprotocol Processor IMP
PDF  47 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TS68302VR16 Datasheet(HTML) 28 Page - ATMEL Corporation

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28
TS68302
2117A–HIREL–11/02
Note:
1. This also applies when SPCLK is inverted by CI in the SPMODE register. The enable signals for the slaves may be imple-
mented by the parallel I/O pins.
2. See Figure 22.
Figure 22. Serial Communication Port Timing Diagram
Table 18. AC Electrical Specifications - Serial Communication Port
(2) f = 16.67 MHz
Num.
Parameter
Min
Max
Unit
250
SPCLK clock output period
4
64
clks
251
SPCLK clock output rise/fall time
15
ns
252
Delay from SPCLK to transmit
(1)
040
ns
253
SCP receive setup time
(1)
40
ns
254
SPC receive hold time
(1)
10
ns
1
2
3
4
567
8
12
3
45
6
78
SPCLK
(OUTPUT)
SPTXD
(OUTPUT)
SPRXD
(INPUT)
250
252
251
253
254
Table 19. AC Electrical Specifications - Idle Timing(3) f = 16.67 MHz All timing measurements, unless otherwise specified,
are referenced to the L1CLK at 50% point of VDD
Num.
Parameter
Min
Max
Unit
260
L1CLK (IDL clock) frequency
(1)
6.66
MHz
261
L1CLK width low
55
ns
262
L1CLK width high
60
ns
263
L1T x D, L1RQ, SDS1-SDS2 rising/falling time
20
ns
264
L1SY1 (sync) setup time (to L1CLK falling edge)
30
ns
265
L1SY1 (sync) hold time (to L1CLK falling edge)
50
ns
266
L1SY1 (sync) inactive before 4th L1CLK
0
ns
267
L1T x D active delay (from L1CLK rising edge)
0
75
ns
268
L1T x D to high impedance (from L1CLK rising edge)
(2)
050
ns
269
L1R x D setup time (to L1CLK falling edge)
50
ns
270
L1R x D hold time (from L1CLK falling edge)
50
ns
271
Time between successive IDL syncs
20
L1CLK
272
L1RQ valid before falling edge of L1SY1
1
L1CLK
273
L1GR setup time (to L1SY1 falling edge)
50
ns



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