TS68302VR16 datasheet(25/47 Pages) ATMEL

25 / 47 page

TS68302

2117A–HIREL–11/02

Notes:

1. For loading capacitance less than or equal to 50 pF, subtract 4 ns from the maximum value given.

2. This specification is valid only when the ADCE or WPVE bits in the SCR are set.

3. See Figure 17.

4. Specs 172-178 do not have diagrams. However, similar diagrams for AS are shown as 25-11-13-14-17-20A and 29.

Figure 17. Internal Master Chip-select Timing Diagram

Notes:

1. The minimum value must be met to guarantee write protection operation.

2. This specification is valid when the DCE or WPVE bits in the SCR are set.

3. Also applies after a timeout of the hardware watchdog.

4. See Figure 18

176

tCSNRWI

CS negated to R/W invalid

(4)

177

CSARWL

CS asserted to R/W low (write)

(4)

178

CSNDII

CS negated to data in invalid (hold time on read)

(4)

0ns

Table 13. AC Electrical Specifications - Chip-select Timing Internal Master(3) f = 16.67 MHz (Continued)

Num.

Symbol

Parameter

Min

Max

Unit

CLKO

(OUTPUT)

IACK1,IACK6,

CS0-CS3

IACK7

DTACK

(OUTPUT)

BERR

(OUTPUT)

150

151

152

153

156

155

157

158

154

Table 14. AC Electrical Specifications - Chip-select Timing External Master

(4) f = 16.67 MHz

Num.

Symbol

Parameter

Min

Max

Unit

154

CLDTKL

Clock low to DTACK low (1-6 wait states)

160

tASLCSL

AS low to CS low

161

ASHCSH

AS high to CS high

162

AVASL

Address valid to AS Low

163

tRWVASL

R/W valid to AS Low

(1)

164

ASHAI

AS negated to Address hold time

165

ASLDTKL

AS low to DTACK low (0 wait state)

167

tASHDTKH

AS high to DTACK high

168

ASLBERL

AS low to BERR low

(2)

169

ASHBERH

AS high to BERR high

(2)(3)

TS68302VR16 Datasheet(PDF) 25 Page - ATMEL Corporation

TS68302VR16 Datasheet(HTML) 25 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL