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CS5127 Datasheet(PDF) 12 Page - Cherry Semiconductor Corporation

Part # CS5127
Description  Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable
PDF  24 Pages
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Manufacturer  CHERRY [Cherry Semiconductor Corporation]
Direct Link  http://www.cherrycorp.com/
Logo CHERRY - Cherry Semiconductor Corporation

CS5127 Datasheet(HTML) 12 Page - Cherry Semiconductor Corporation

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Applications Information: continued
The zero frequency due to the output capacitor ESR is
given as
= 4.8 kHz.
The double pole frequency of the power output stage is
=
= 1.95 kHz.
The ESR zero approximately cancels one of the poles, and
the total phase shift is limited to 90. Bode plots are provid-
ed below.
Figure 7: Bode plot of gain response for VOUT/VCONTROL.
Figure 8: Bode plot of phase response for VOUT/VCONTROL.
This uncompensated system is stable, but the low gain will
result in poor DC accuracy, and the low cutoff frequency
will result in poor transient response. Note that we have
not yet included the gain factor from the feedback resistor
divider. This factor will further reduce the overall system
gain.
By adding the two pole, one zero compensation network
shown in figure 6, we can maximize the DC gain and push
out the crossover frequency. The transfer function for the
compensation network is
=
This can be rewritten in terms of pole and zero frequencies
and a gain constant A.
=
where
fZ =
fP =
and A = R1 C2
Note that, due to the first s term in the denominator, a pole
is located at f = 0. This will provide the maximum DC
gain.
The optimum performance can be obtained by choosing fZ
equal to the output double pole frequency and setting fP to
approximately half of the switching frequency. Gain fac-
tors can be chosen somewhat arbitrarily.
Values between
1E-6½F and 20E-6½F are practical. We then have a set of
equations that can be solved for component values:
C1 R1 =
[ - ],C1R2= ,C2=
Since there are only three equations, we must arbitrarily
choose one of the components. One option is to set the
value of R1 fairly large. This provides a high impedance
path between the VFB pin and the COMP pin.
For our design, we have fZ = the double pole frequency =
1.95 kHz and fP = fOSC/2 = 100kHz. LetÕs arbitrarily choose
R1 = 4.7K. Then we solve the first equation for C1 and
obtain C1 = 17nF. Use a standard value of 22 nF.
We next solve for R2. With C1 =22 nF, R2= 72½. Use a
standard value of 75½.
We can choose a gain factor from somewhere in the
middle of our range and solve for C2. If A = 10E-6½F, we
have
C2 = 2.1 nF. Use a standard value of 2.2 nF.
A
R1
1
2¹fP
1
fP
1
fZ
1
2¹
1
2¹ C1R2
1
(2¹ C1 (R1 + R2))
s/(2¹fZ + 1)
-A s ((s/2fP) + 1)
VCONTROL
VFB
s C1(R1 + R2) + 1
-s C2 R1(s C1 R2 + 1)
VCONTROL
VFB
-270.0
1
Frequency (Hz)
-90
-180
0
90
102
103
104
106
105
10
107
-60.0
1
Frequency (Hz)
-20
-40
0
20
102
103
104
106
105
10
107
R + R1
LC(R + RC)
1
(2¹)
1
(2¹CRC)
1 + s(3.3E-5)
s2(2.772E-9) + s(2.902E-5) + 0.42



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