CS5127 datasheet(14/24 Pages) CHERRY

14 / 24 page

Applications Information: continued

IC. This heat is transferred to the surface of the IC package,

but a thermal gradient exists due to the thermal properties

of the package molding compound. The magnitude of this

thermal gradient is denoted in manufacturerÕs data sheets

QJA , or junction-to-air thermal resistance. The on-chip

junction temperature can be calculated if

QJA , the air tem-

perature at the ICÕs surface and the on-chip power

dissipation are known:

TJ = TA + (QJA ´ P)

TJ and TA are given in degrees centigrade, P is IC power

dissipation in watts and

QJA is thermal resistance in

degrees centigrade per watt. Junction temperature should

be calculated for all semiconductor devices to ensure they

are operated below the manufacturerÕs maximum junction

temperature specification. If any componentÕs temperature

exceeds the manufacturerÕs maximum specification, some

form of heatsink will be required.

Heatsinking will improve the thermal performance of any

IC. Adding a heatsink will reduce the magnitude of

QJA by

providing a larger surface area for heat transfer to the sur-

rounding air. Typical heat sinking techniques include the

use of commercial heatsinks for devices in TO-220 pack-

ages, or printed circuit board techniques such as thermal

bias and large copper foil areas for surface mount pack-

ages.

When choosing a heatsink, it is important to break

QJA

into several different components.

QJA = QJC + QCS + QSA

where all components of

QJA are given in ¡C/W.

QJC is the thermal impedance from the junction to the sur-

face of the package case. This parameter is also included in

manufacturerÕs data sheets. Its value is dependent on the

mold compound and lead frames used in assembly of the

semiconductor device in question.

QCS is the thermal impedance from the surface of the case

to the heatsink. This component of the thermal impedance

can be modified by using thermal pads or thermal grease

between the case and the heat sink. These materials replace

the air gap normally found between heatsink and case with

a higher thermal conductivity path. Values of

QCS are

found in catalogs published by manufacturers of heatsinks

and thermal compounds.

Finally,

QSA is the thermal impedance from the heatsink to

ambient temperature.

QSA is the important parameter

when choosing a heatsink. Smaller values of

QSA allow

higher power dissipation without exceeding the maximum

junction temperature of the semiconductor device. Values

QSA are typically provided in catalogs published by

heatsink manufacturers.

The basic equation for selecting a heatsink is

PD =

where PD is on-chip power dissipation in watts, TJ is junc-

tion temperature in ¡C, TA is ambient temperature in¡C,

and thermal impedance

QJC , QCS , and QSA are in¡C/W.

All these quantities can be calculated or obtained from data

sheets. The choice of a heatsink is based on the value of

QSA required such that the calculated power dissipation

does not cause junction temperature to exceed the manu-

facturerÕs maximum specification.

Switching regulators generate noise a consequence of the

large values of current being switched on and off in normal

operation. Careful attention to layout of the printed circuit

board will usually minimize noise problems. Layout guide-

lines are provided in the next section. However, it may be

necessary in some cases to add filter inductors or bypass

capacitors to the circuitry to achieve the desired perfor-

mance.

The following guidelines should be observed in the layout

of PC boards for the CS5127:

1. Connect the PGND lead to the external ground with a

wide metal trace.

2. Connect both LGND and PGND together with a wide

trace as close to the IC as possible.

3. Make all ground connections to a common ground

plane with as few interruptions as possible. Breaks in

the ground plane metal should be made parallel to an

imaginary line between the supply connections and the

load.

4. Connect the ground side of the COMP lead capacitors

back to LGND with separate traces.

5. Place the VFFB lead capacitors as close to the VFFB leads

as possible.

6. Place the 5V line bypass capacitors as close to the

switch FETs as possible.

7. Place the output capacitor network as close to the load

as possible.

8. Route the GATE lead signals to the FET gates with a

metal trace at least 0.025 inches wide.

9. Use wide straight metal traces to connect between the

5V line and FETs, between FETs and inductors and

between inductors and loads to minimize resistance in

the high current paths. Avoid sharp turns, loops and

long lengths.

Layout Considerations

EMI Management

TJ - TA

QJC + QCS + QSA

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