AD9625 datasheet(39/56 Pages) AD

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Data Sheet

AD9625

Table 30. User Test Pattern 2 LSB Register, Address 0x01B (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 2 least significant byte. Note: these bits are used only when Register 0x00D,

Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.

Table 31. User Test Pattern 2 MSB Register, Address 0x01C (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 2 most significant byte. Note: these bits are used only when Register 0x00D,

Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.

Table 32. User Test Pattern 3 LSB Register, Address 0x01D (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 3 least significant byte. Note: these bits are used only when Register 0x00D,

Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.

Table 33. User Test Pattern 3 MSB Register, Address 0x01E (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 3 most significant byte. Note: these bits are used only when Register 0x00D,

Bits[3:0] is in user input mode (Register 0x00D[3:0] = 1000).Otherwise, these bits are ignored.

Table 34. User Test Pattern 4 LSB Register, Address 0x01F (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 4 least significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input

mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.

Table 35. User Test Pattern 4 MSB Register, Address 0x020 (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

User Test Pattern 4 most significant byte. Note: these bits are used only when Register 0x00D, Bits[3:0] is in user input

mode (Register 0x00D[3:0] = 1000). Otherwise, these bits are ignored.

Table 36. Synthesizer PLL Control Register, Address 0x021 (Default = 0x00)

Bit No.

Access

Bit Description

[7:5]

Unused.

1 = force power-down of VCO LDO

Reserved for future use.

[2:0]

Unused.

Table 37. ADC Analog Input Control Register, Address 0x02C (Default = 0x00)

Bit No.

Access

Bit Description

[7:3]

Unused.

Set function on VMON pin.

0: unused.

1: allow customer to apply external reference on VMON pin.

[1:0]

Unused.

Table 38. SYSREF Control Register, Address 0x03A (Default = 0x00)

Bit No.

Access

Bit Description

SYSREF status bit replaces the LSB from the converter.

0: normal mode.

1: SYSREF status bit replaces the LSB.

SYSREF status bit flag reset. To use the flags, Register 0x03A, Bit 1 must be set to high.

0: normal flag operation.

1: SYSREF status bit flags held in reset.

Unused.

SYSREF± transition selection.

0: SYSREF± is valid on low to high transitions using selected CLK edge.

1: SYSREF± is valid on high to low transitions using selected CLK edge.

Rev. 0 | Page 39 of 56

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