AD9625 datasheet(13/56 Pages) AD

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Data Sheet

AD9625

Pin No.

Mnemonic

Type

Description

ADC Analog Input and Outputs Pins

VIN+

Input

Differential Analog Input, True.

A10

VIN−

Input

Differential Analog Input, Complement.

VCM

Output

Analog Input, Common Mode (0.525 V).

VMON

Output

CTAT Voltage Monitor Output (Diode Temperature Sensor).

JESD204B High Speed Power and Ground Pins

N1, N6, N11, P1, P6, P11

DRVDD1

Power

Serial Digital Power Supply (1.3 V).

M1 to M10, M13, M14, P12

DRGND

Ground

Digital Driver Ground Supply. These pins connect to the

digital driver ground plane.

N13, N14

DRVDD2

Power

Power Supply (2.5 V) Reference Clock Divider, SYNCINB±,

DIVCLK±.

M11

DRVDD1

Power

Power Supply (1.3 V) Reference Clock Divider, VCO, and

Synthesizer.

N12

VP_BYP

Input

Voltage Bypass.

DNC

N/A

Do Not Connect. Do not connect to this pin.

JESD204B High Speed Serial I/O Pins

J14

SYSREF+

Input

System Reference Chip Synchronization, True.

K14

SYSREF−

Input

System Reference Chip Synchronization, Complement.

SYNCINB+

Input

Synchronization, True. SYNCINB LVDS input (active low, true).

SYNCINB−

Input

Synchronization, Complement. SYNCINB LVDS input (active

low, complement).

N10

SERDOUT[0]+

Output

Lane 0 CML Output Data, True.

P10

SERDOUT[0]−

Output

Lane 0 CML Output Data, Complement.

SERDOUT[1]+

Output

Lane 1 CML Output Data, True.

SERDOUT[1]−

Output

Lane 1 CML Output Data, Complement.

SERDOUT[2]+

Output

Lane 2 CML Output Data, True.

SERDOUT[2]−

Output

Lane 2 CML Output Data, Complement.

SERDOUT[3]+

Output

Lane 3 CML Output Data, True.

SERDOUT[3]−

Output

Lane 3 CML Output Data, Complement.

SERDOUT[4]+

Output

Lane 4 CML Output Data, True.

SERDOUT[4]−

Output

Lane 4 CML Output Data, Complement.

SERDOUT[5]+

Output

Lane 5 CML Output Data, True.

SERDOUT[5]−

Output

Lane 5 CML Output Data, Complement.

SERDOUT[6]+

Output

Lane 6 CML Output Data, True.

SERDOUT[6]−

Output

Lane 6 CML Output Data, Complement.

SERDOUT[7]+

Output

Lane 7 CML Output Data, True.

SERDOUT[7]−

Output

Lane 7 CML Output Data, Complement.

P14

DIVCLK+

Output

Divide-by-4 Reference Clock LVDS, True.

P13

DIVCLK−

Output

Divide-by-4 Reference Clock LVDS, Complement.

Digital Supply and Ground Pins

D1 to D3, F1 to F3, H1 to H3, K1 to K2

DVDD1

Power

ADC Digital Power Supply (1.3 V).

F5, G5

DVDDIO

Power

Digital I/O Power Supply (2.5 V).

SPI_VDDIO

Power

SPI Digital Power Supply (2.5 V).

DVDD2

Power

ADC Digital Power Supply (2.5 V).

E1 to E3, G1 to G3, J1 to J3, L1, L5 to L9

DGND

Ground

Digital Control Ground Supply. These pins connect to the

digital ground plane.

DNC

N/A

Do Not Connect. Do not connect to this pin. Leave this pin

floating.

Rev. 0 | Page 13 of 56

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