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Data Sheet

AD9625

ADC Output Control Bits on JESD204B Samples

When N' = 16 and the ADC resolution is 12, there are four

spare bits available per sample. Two of these spare bits can be

used as control bits in Location 2 to Location 1 of the sample,

depending on the configuration options. The control bits are set

in Register 0x072, Bits[7:6].

•

00: no control bits sent per sample (CS = 0).

•

01: one control bit sent per sample, overrange bit enabled,

(CS = 1).

•

10: two control bits sent per sample, overrange + time

stamped SYSREF control bit (marks the sample of a rising

edge seen on the SYSREF± pin), (CS = 2). Use of the

SYSREF control bit (CS = 2) time stamps a particular

analog sample that is seen coincident with a rising signal

on the SYSREF± pins.

Bits[5:4] in Register 0x061 control the JESD204B interface test

injection points.

•

00: 16-bit test generation data injected at the sample input

to the link.

•

01: 10-bit test generation data injected at the output of the

8-bit/10-bit encoder (at the input to PHY).

•

10: 8-bit test generation data injected at the input of the

scrambler.

•

11: reserved.

Bits[3:0] in Register 0x061 determine the type of test patterns

that are injected, as follows:

•

0000: normal operation (test mode disabled).

•

0001: alternating checkerboard.

•

0010: 1/0 word toggle.

•

0011: PN sequence: long (x23 + x18 + 1).

•

0101: continuous/repeat user test mode; most significant

bits from 16-bit user pattern (1, 2, 3, 4) are placed on the

output for one clock cycle and then repeated. (Output user

pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ….)

•

0110: single user test mode; most significant bits from the

16-bit user pattern (1, 2, 3, 4) placed on the output for one

clock cycle and then outputs all zeros. (Output user

pattern: 1, 2, 3, 4, then output all zeros.)

•

0111: Ramp output (dependent on test injection point and

number of bits, N).

•

1000: modified RPAT test sequence.

•

1001: unused.

•

1010: JSPAT test sequence.

•

1011: JTSPAT test sequence.

•

1100 to 1111: unused.

JESD204B APPLICATION LAYERS

The AD9625 supports the following application layer modes via

•

0100: fS × x mode which supports line rates at integer

multiples of the sample rates

•

1000: single DDC mode, high bandwidth mode (only

DDC 0 used)

•

1001: single DDC mode, low bandwidth mode (only

DDC 0 used)

•

1010 to 1011: unused

•

1100: dual DDC mode, high bandwidth mode (both

DDC 0 and DDC 1 used)

•

1101: dual DDC mode, low bandwidth mode (both DDC 0

and DDC 1 used)

•

1110: dual DDC mode, mixed bandwidth mode (DDC 0

high bandwidth mode, DDC 1 low bandwidth mode,

samples repeated)

fS × 2, fS × 4, fS × 8 Modes

The JESD204B low multiplier mode application layer adds a

rate conversion on top of a JESD204B transmitter/receiver with

the following configuration parameters: M = 1; L = 8; S = 4;

F = 1; N = 16; N' = 16; CS = 0; CF = 0; SCR = 0, 1; HD = 1;

K = reference JESD204B specification.

In this mode, there are five actual samples per frame and

scrambling can be optionally enabled in the JESD204B

interface. The transmit portion of the low multiplier mode

JESD204B application layer is shown in Figure 46.

The first step in this application layer is where 12-bit ADC

samples are divided into six bytes.

To allow the line rate of the JESD204B interface to map directly

into an integer of the converter sample rate, a four to five rate

conversion takes place to group the 12-bit ADC samples into

blocks of five samples. During this rate conversion, for every

five 12-bit ADC sample, an extra user defined, 4-bit nibble is

appended to create a 64-bit frame. Next, the 64-bit low

multiplier frame maps into the four 16-bit JESD204B samples.

The most significant 16-bits of the 64-bit low multiplier frame

map to the oldest 16-bit JESD204Bsample and the least

significant 16-bits of the 64-bit low multiplier frame map to the

most recent 16-bit JESD204B sample.

The receive portion of the fS × 2 JESD204B application layer is

shown in Figure 47.

Rev. 0 | Page 31 of 56

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